Method for forming fin field effect transistor

Abstract

Disclosed is a formation method for a fin type field effect transistor. The formation method comprises the steps of providing a semiconductor substrate, wherein a plurality of fin parts and a mask layer positioned on the top parts of the fin parts are arranged on the semiconductor substrate, and first grooves arranged parallel to the fin parts and second grooves arranged perpendicular to the fin parts are formed between adjacent fin parts; forming an isolating layer, wherein the surface of the isolating layer is flush with the surface of the mask layer; performing primary back etching on the isolating layer; performing etching on the mask layer to expose a part of surfaces at the two ends of the fin parts; forming a first patterned mask layer to expose the surfaces at the two ends of the fin parts; etching the fin parts and forming circular angles at the two ends of the fin parts; removing the first pattered mask layer, and forming a second patterned mask layer to cover the isolating layer in the second grooves; performing secondary back etching on the isolating layer; removing the mask layer to form a gate which transversely crosses the fin parts and a pseudo gate which is positioned on the surface of the isolating layer, wherein the pseudo gate and the gate are in parallel; and forming side walls on the side wall surfaces of the gate and the pseudo gate. By virtue of the formation method, the performance of the formed fin type field effect transistor can be improved.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for forming a fin field effect transistor. Background technique [0002] With the continuous development of semiconductor process technology, the process node is gradually reduced, and the gate-last (gate-last) process has been widely used to obtain an ideal threshold voltage and improve device performance. However, when the feature size (CD, Critical Dimension) of the device is further reduced, even if the gate-last process is adopted, the structure of the conventional MOS field effect transistor can no longer meet the requirements for device performance, and the fin field effect transistor (Fin FET) as a conventional Device substitution has received extensive attention. [0003] In order to further improve the performance of fin field effect transistors, stress engineering is introduced into the transistor manufacturing process. After the source and drain groov...

AI Technical Summary

Problems solved by technology

Because in the prior art, the height of the shallow trench isolation structure between the fins is lower than that of the fins, there is no sidewall on one side of the source and drain grooves formed at both ends of the fins, and the source and drain grooves When the stress material is formed by epitaxy, the stress material is prone to collapse and other problems, resulting in the stress release of the stress material, so that the effect of stress applied to the transistor channel region becomes worse

And the stress layer in the source and drain grooves is easy to bridge with the dummy gate on the surface of the shallow trench isolation structure, which affects the performance of the formed fin field effect transistor

[0005] The performance of the fin field effect transistor formed by the existing technology needs to be further improved

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