A method to increase the number of chip simultaneous measurement

Abstract

The invention discloses a method for improving the number of chip simultaneous measurement, which comprises the following steps: (1) placing a BIST circuit in the space between the dicing grooves between the chips; (2) connecting the BIST circuit to the surrounding chips through a data bus connection; (3) the automatic test equipment sends a control signal to the BIST circuit, selects a plurality of connected chips to be tested, and performs multi-chip testing; (4) the BIST circuit feeds back the test results and the state of the data register to the automatic test equipment, and the automatic test equipment Determine the PASS / FAIL status of each test chip and the failure mode and location inside the chip according to the test results and data registers, so as to realize multi-chip simultaneous testing; (5) After the test is completed, when the silicon wafer is cut and picked, the BIST The circuit is removed from the scribe slot. The present invention provides a method for increasing the number of simultaneous chip measurements, which can realize multi-chip simultaneous measurement without increasing additional chip area.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for improving the number of simultaneous measurements of chips. Background technique [0002] With the improvement of circuit integration and circuit complexity, the test cost of automatic test equipment is getting higher and higher. In addition, due to the constraints of the test environment of the automatic test equipment, it will be more and more difficult to realize the high-speed mixed-signal automatic test equipment, and it is impossible for a large number of signals in the chip to lead out to the automatic test equipment for testing through the PAD. [0003] BIST circuit can be used to provide self-test function, so as to reduce the dependence of chip test on automatic test equipment, which has the advantages of reducing test cost, improving error coverage, shortening test time, and independent testing. [0004] The currently known BIST circuit is built on...

AI Technical Summary

Problems solved by technology

[0004] The currently known BIST circuit is built on the chip during the test process, and the BIST circuit part is removed after the test is completed, as shown in the attached figure 1 As shown; this BIST circuit has the following defects: (1) BIST circuit needs to take extra chip area, thereby causes the increase of chip area, causes the waste of production cost and process; (2) builds up on the BIST circuit on the chip, only Can be tested for the corresponding chip, but cannot be connected with other chips, so it is impossible to test multiple chips at the same time, and it cannot effectively save test time

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