Method for keeping consistent phase of frequency division clock and frequency division circuit

Abstract

The invention discloses a method for keeping a consistent phase of a frequency division clock and a frequency division circuit. The method comprises the following steps: communicating a D input end of the last stage register of a first frequency divider with the D input end of the last stage register of a second frequency divider, wherein the first frequency divider is located at the outside of a curing module, and the second frequency divider is located in the curing module; performing frequency division on a source clock signal through the first frequency divider and the second frequency divider, outputting a first frequency division signal from a Q output end of the last stage register of the first frequency divider, and outputting a second frequency division signal from the Q output end of the last stage register of the second frequency divider, wherein the phase of the first frequency division signal is consistent with the phase of the second frequency division signal.

Description

technical field [0001] The invention relates to frequency division technology in the field of integrated circuits, in particular to a method and a frequency division circuit for keeping phases of frequency division clocks consistent. Background technique [0002] With the rapid development of consumer electronics, the functions of chips are becoming more and more complex, and the scale is also increasing. The modules integrated in the chip are also getting larger and more complex, such as processors and memory modules. In order to facilitate the comprehensive realization of the whole chip, these large modules are usually integrated into the full-chip netlist (netlist) in a separate hardening manner. [0003] In order to adapt to different application scenarios of the chip, some large modules in the chip often have a variety of clock sources, including high-frequency clocks for high performance and low-frequency clocks for low power consumption. Among them, these large modu...

AI Technical Summary

Problems solved by technology

Since there is data interaction between these modules based on frequency-divided clocks, as the layout and wiring of the whole chip become larger and larger, the clocks of the two registers with data interaction are generated by two different frequency dividers. The phase of the divided clock generated by the frequency converter is consistent, which becomes the key to the correct function of the module. For this problem, the related technology has not yet solved

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