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integrated circuit structure

A technology for integrated circuits and power grids, applied in circuits, electrical components, electrical solid devices, etc., and can solve problems such as deteriorating resistance values ​​and long word lines.

Active Publication Date: 2020-06-09
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Second, it is also necessary to connect each wordline to more rows of SRAM cells, which results in longer wordlines and thus worse resistance values

Method used

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  • integrated circuit structure
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Embodiment Construction

[0098] The following disclosure provides many different embodiments, or examples, for implementing the different features of the present disclosure. The following disclosure describes specific examples of various components and their arrangements to simplify the description. Of course, these specific examples are not intended to be limiting. For example, if the disclosure describes that a first feature is formed on or over a second feature, it means that it may include an embodiment in which the above-mentioned first feature is in direct contact with the above-mentioned second feature, and may also include additional features. Embodiments in which a feature is formed between the first feature and the second feature such that the first feature and the second feature may not be in direct contact. In addition, the same reference signs and / or symbols may be reused in different examples in the following publications. These repetitions are for simplicity and clarity and are not in...

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Abstract

The present disclosure relates to an integrated circuit structure. An integrated circuit structure includes a static random access memory cell including a read port and a write port. The write port includes a first pull-up MOS device and a second pull-up MOS device, a first pull-down MOS device and a second pull-down MOS device, and the first pull-up MOS device. The pull-up MOSFET and the second pull-up MOSFET form an interleaved latch inverter. The integrated circuit structure also includes a first metal layer with a bit line, a first CVdd wire and a first CVss wire located in the first metal layer. A second metal layer is located on the first metal layer. A write word line is located in the second metal layer. A third metal layer is located on the second metal layer. A read word line is located in the third metal layer.

Description

technical field [0001] The present disclosure relates to an integrated circuit device, and more particularly, to an integrated circuit structure. Background technique [0002] Static Random Access Memory (SRAM) is often used in integrated circuits. A static random access memory cell (SRAM cell) has the advantage of saving data without refreshing. As the speed of integrated circuits increases, the read speed and write speed of SRAM cells become more important. However, with the shrinking size of the already very small SRAM cells, it is difficult to realize the above requirements. For example, the sheet resistance of the metal wires forming the word lines and bit lines of the SRAM cell becomes higher and higher, and thus increases the word line of the SRAM cell. The resistance-capacitance delay (RC delay) situation with the bit line hinders the improvement of the read speed and the write speed. [0003] Split-word-line type static based on lithography-friendly layout shape...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C11/412G11C11/413
CPCG11C11/412G11C11/413G11C8/16G11C11/419H10B10/12H10B10/18G11C11/417Y10S257/903H01L23/528
Inventor 廖忠志
Owner TAIWAN SEMICON MFG CO LTD