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Method for self-inspection during wafer test and wafer test fixture thereof

A wafer testing and wafer technology, which is used in the testing of single semiconductor devices, measuring devices, measuring electrical variables, etc., and can solve problems such as damage to small units of equipment, failure to detect damage, and uneven production.

Active Publication Date: 2019-09-17
EVERDISPLAY OPTRONICS (SHANGHAI) CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] 1. Since the complete self-inspection of the test machine takes a long time, the factory only does it during regular maintenance or when there is an abnormality in online production. During this period, the equipment may also be damaged in a small unit but not found
[0007] 2. The self-verification method provided by the equipment manufacturer may be defective, and no damage is detected
[0008] 3. Regular maintenance may not be completed due to personnel negligence
This method mainly has the following disadvantages: the calibration circuit on the tool is of high specification, if it is not calibrated and confirmed before production, it will cause misjudgment of the program and lead to production failure

Method used

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  • Method for self-inspection during wafer test and wafer test fixture thereof
  • Method for self-inspection during wafer test and wafer test fixture thereof
  • Method for self-inspection during wafer test and wafer test fixture thereof

Examples

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Embodiment Construction

[0079] Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals denote the same or similar structures in the drawings, and thus their repeated descriptions will be omitted.

[0080] The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided in order to give a thorough understanding of embodiments of the invention. However, those skilled in the art will appreciate that the technical solutions of the present invention may be practiced without one or more of the specific...

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PUM

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Abstract

The invention provides a wafer test self-detection method and a wafer test fixture thereof. The method comprises the measurement step: A probe sets are contacted with multiple crystal grains of at least one measurement area of a wafer, each probe set comprises at least one probe and the probe set is electrically connected with one crystal grain, and the probe sets measure the electrical signal parameters of each crystal grain in the measurement area for multiple times; and the judgment step: whether the equipment difference percentage value G of the number A of the probe sets is greater than or equal to a preset percentage threshold H is judged according to the standard exceeding frequency F that the measurement error percentage E of each probe set and other probe sets exceeds the preset standard range, and the probe sets of which the equipment difference percentage value G is greater than or equal to the preset percentage threshold H are unqualified. According to the wafer test self-detection method and the wafer test fixture thereof, the state of the probe sets can be continuously monitored in production so that the interference of human factors can be eliminated and production stagnation caused by line abnormity can be reduced.

Description

technical field [0001] The invention relates to the field of crystal testing, in particular to a method for self-testing during wafer testing and a wafer testing tool. Background technique [0002] Now there are many products that require accurate voltage to match the application, and most of them currently use destructive electrical methods to correct for differences in wafer production. [0003] figure 1 A schematic diagram of a test wafer for a prior art wafer test fixture. An existing wafer test tool includes a wafer test tool 20', and the wafer test tool 20' has a first probe set 21', a second probe set 22', a third probe set 23 ' and the fourth probe set 24'. The four probe sets of the wafer test fixture 20' test the die in the measurement area 10' of the wafer 1'. During testing, the wafer is fixed on a chuck with vacuum suction, and gold wires are used to make multiple hair-thin probes on the probe assembly, and multiple solder pads on each die (pad) contact at ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G01R31/26G01R35/00
Inventor 范智翔
Owner EVERDISPLAY OPTRONICS (SHANGHAI) CO LTD