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Continued fraction storage-based integrated circuit test data compression method

A technology for testing data and integrated circuits, applied in the direction of measuring electricity, measuring devices, measuring electrical variables, etc., can solve the problem of increased hardware overhead of counters, achieve the effect of reducing hardware overhead and expanding run length

Active Publication Date: 2017-09-08
上海沃时电子有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Its decompression structure contains 2 counters. When the run length is large, the hardware overhead of the corresponding counter in the decompression structure increases significantly.

Method used

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  • Continued fraction storage-based integrated circuit test data compression method
  • Continued fraction storage-based integrated circuit test data compression method
  • Continued fraction storage-based integrated circuit test data compression method

Examples

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Embodiment Construction

[0040] The specific embodiment of the present invention will be further described below in conjunction with accompanying drawing:

[0041] like figure 1 It can be seen that the integrated circuit test data compression method based on continued fraction storage of the present invention comprises the following steps:

[0042] A, adopt automatic test pattern generation tool ATPG, generate the complete test set T of definite, described complete test set T is made up of the test vector of finite fixed width, record the width of this test vector;

[0043] Common knowledge: A single test vector includes a finite number of definite bits and a finite number of irrelevant bits. The position of the definite bit in the current test vector is not fixed, and the definite bit is embodied as a binary number 0 or 1; the position of the unrelated bit in the current test vector is not fixed. Fixed, after the irrelevant bits are filled with 0 or 1, it has no effect on the test results of the int...

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Abstract

The invention provides a continued fraction storage-based integrated circuit test data compression method. With the method adopted, further compression of test data can be realized. According to the method of the invention, data are read from a test data packet S in turn according to bits; a don't care bit is filled with 0 or 1 according to adjacent determined bits, so that the length of an obtained run can be the largest, and the test data packet S are converted into a plurality of runs; a set of compression codes is obtained according to two adjacent runs, and is added into a compression data packet; and the compression codes consist of three parts, namely, a dual-run code, a common divisor code and a continued fraction code. The invention also discloses a corresponding decoding program.

Description

technical field [0001] The invention relates to an integrated circuit test technology, in particular to a test data compression method in a built-out self-test (Built-Out Self-Test, BOST) method for a system chip (System-on-a-Chip, SoC). Background technique [0002] In SoC design, higher and higher circuit density leads to a sharp increase in the amount of test data. Larger test data sizes not only require higher memory requirements, but also increase test time. The ITRS 2013 report shows that the minimum test data volume for SOC-CP-ConsumerSOC testing has increased by nearly 4 times in 10 years, and the minimum compression ratio has increased by nearly 6 times in 10 years. Test data compression techniques solve this problem by reducing the amount of test data without affecting the overall performance of the system. [0003] Coding compression technology uses shorter code words than the original test data to store test data and realize the compression of test data. It is ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G01R31/3183
CPCG01R31/318307G01R31/318335
Inventor 吴海峰江健生程一飞吴琼詹文法
Owner 上海沃时电子有限公司
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