Chip package and method for forming the same

A technology for a chip package and a manufacturing method, which is applied to the manufacturing of semiconductor/solid-state devices, semiconductor devices, and electric solid-state devices, etc., can solve the problems of reduced quality and reliability of chip packages, reduced thickness and width of wires, and circuit failures. , to achieve the effect of eliminating electromigration phenomenon, improving quality and reliability

CN107146795AInactive Publication Date: 2017-09-08XINTEC INC
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Publication Date
2017-09-08
Estimated Expiration
Not applicable · inactive patent

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Abstract

The invention provides a chip package and a method for forming the same. A chip package including a substrate is provided. A sensing region or device region of the substrate is electrically connected to a conducting pad. A first insulating layer is disposed on the substrate. A redistribution layer is disposed on the first insulating layer. A first portion and a second portion of the redistribution layer are electrically connected to the conducting pad. A second insulating layer conformally extends on the first insulating layer, and covers side surfaces of the first portion and the second portion. A protection layer is disposed on the second insulating layer. A portion of the second insulating layer is located between the protection layer and the first insulating layer. The quality and the reliability of the chip package can be greatly improved.
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Description

technical field

[0001] The present invention relates to a semiconductor packaging technology, in particular to a chip package and a manufacturing method thereof. Background technique

[0002] The chip packaging process is an important step in the process of forming electronic products. In addition to protecting the chip therein from external environment pollution, the chip package also provides an electrical connection path between the electronic components inside the chip and the outside world. For example, there are wires in the chip package to form a conductive path. As electronic products gradually develop toward miniaturization, the size of chip packages is also gradually reduced.

[0003] However, when the size of the chip package shrinks, the thickness and width of the wires become smaller, and the distance between the wires also becomes narrower, so that circuit faults are likely to occur in the densely populated circuit area. For example, electromigration and / or G...

Examples

Embodiment Construction

[0014] The fabrication and use of the embodiments of the present invention will be described in detail below. It should be noted, however, that the present invention provides many applicable inventive concepts, which can be embodied in a wide variety of specific forms. The specific embodiments discussed herein are merely specific ways to make and use the invention, and do not limit the scope of the invention. Furthermore, repeated reference numerals or designations may be used in different embodiments. These repetitions are only for the purpose of simply and clearly describing the present invention, and do not represent any relationship between the different embodiments and / or structures discussed. Furthermore, when it is mentioned that a first material layer is located on or above a second material layer, it includes the situation that the first material layer is in direct contact with the second material layer or is separated by one or more other material layers.

[0015] ...