FPGA-based edge detection method, system and clock data recovery circuit

Abstract

The invention discloses an FPGA-based edge detection method, system and clock data recovery circuit, and relates to the technical field of communication. The method includes the following steps: using a local reference clock to perform oversampling and delay processing on the received data signal, and generating a rising edge pulse signal and a falling edge pulse signal based on the oversampling and delay processing data signal, the rising edge pulse signal includes Several rising edge pulses, the falling edge pulse signal includes several falling edge pulses; the number N of local reference clock cycles after each rising edge pulse and the number M of local reference clock cycles after each falling edge pulse are counted respectively; when When M-N is greater than the set threshold, it is determined that the rising edge pulse is a valid rising edge pulse, and when N-M is greater than the threshold, it is determined that the falling edge pulse is a valid falling edge pulse. The invention can detect effective rising edge pulses and falling edge pulses, and improves the accuracy and reliability of data signal sampling.

Description

[0001] The invention relates to the technical field of communication, in particular to an edge detection method, system and clock data recovery circuit. Background technique [0002] With the development of communication technology and electrical signal processing technology, serial data communication is widely used in telecommunications, optical transceivers, data storage area networks and wireless products, and the transmission rate is getting faster and faster. In serial data communication, in order to save overhead, generally only the data signal is transmitted without the clock signal synchronized with the data signal, that is, at the sending end, the clock is embedded into the data, and at the receiving end, clock data recovery (Clock and Data Recovery) is used. The Data Recovery (CDR) circuit extracts the clock from the received data, and then uses the clock to "retime" the data to eliminate the jitter accumulated during transmission. A CDR circuit based on a phase lock...

AI Technical Summary

Problems solved by technology

A CDR circuit based on a phase locked loop (PLL) can realize phase tracking and synchronization between the local reference clock and data, but for burst signals, the PLL cannot meet the requirements of fast synchronization, and a large phase Changes can cause loss of lock, and the lock time is usually very long, unable to quickly capture the phase change of the received data

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