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CPU for realizing randomization of dynamic instruction sets

A dynamic instruction and randomization technology, applied in the CPU field, can solve the problems of high performance loss and achieve the effect of reducing operating loss and improving the defense effect

Active Publication Date: 2017-09-22
THE PLA INFORMATION ENG UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0009] The purpose of the present invention is to provide a CPU for realizing dynamic instruction set randomization, so as to solve the problem that the current CPU instruction set randomization adopts virtual machine translation or dynamic binary translation to cause large performance loss

Method used

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  • CPU for realizing randomization of dynamic instruction sets
  • CPU for realizing randomization of dynamic instruction sets
  • CPU for realizing randomization of dynamic instruction sets

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Embodiment Construction

[0025] The specific embodiments of the present invention will be further described below in conjunction with the accompanying drawings.

[0026] Current CPU systems such as figure 1 As shown, it includes a processor and a memory. The processor includes registers, processing circuits, data pipelines and decoders. The instruction pipeline reads instructions from the memory and sends the read instructions to the instruction decoder for decoding. The instruction decoder generates control signals in response to the program instructions decoded by the instruction decoder, and the generated control signals control the access of processing circuits and registers.

[0027]The present invention is aimed at CPUs based on RISC architecture. This embodiment uses the OpenRISC project as an example for illustration. The instruction randomization CPU of the present invention is also applicable to CPUs with other RISC instruction architectures. The OpenRISC project provides an open-source RIS...

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Abstract

The invention relates to a CPU for realizing randomization of dynamic instruction sets, and belongs to the technical field of embedded system safety. The CPU is implemented through the following steps of: generating a random number by utilizing a random number generation circuit; sending the generated random number into a register; randomizing an instruction by utilizing a randomization algorithm and the random number; and adding an instruction translation circuit between an instruction fetching stage and a decoding stage, wherein the circuit comprises a selector, the selector responds to a selection signal so as to determine to send a first path of signal or a second path of signal into a decoder, the first path of signal is an instruction in an instruction pipeline in the instruction fetching stage, and the second path of signal is an instruction obtained by the first path of signal according to the random number stored in the register and an anti-randomization algorithm. Under the support of CPU software randomization, the CPU is capable of realizing the randomization and dynamization of kernels and has good defense effect for code injection type attacks; and compared with the instruction randomization realized by using virtual machines or binary systems, the CPU is capable of reducing the operation loss.

Description

technical field [0001] The invention relates to a CPU for realizing randomization of a dynamic instruction set, and belongs to the technical field of embedded system security. Background technique [0002] The Internet of Things (IOT) is an important part of the new generation of information technology, which includes ubiquitous things into the same network, and the security issues that follow have been widely concerned. Hackers can exploit device vulnerabilities to attack, seriously affecting personal privacy, personal payment security, and personal safety. Embedded systems are the supporting technology of IOT, and ensuring the security of embedded systems is an important way to ensure the security of IOT. In the era of the Internet of Things, almost all embedded systems have Internet access capabilities, and the architecture has changed from closed to open, forming an intrusion channel for non-security factors in the Internet to embedded systems. Code injection attack is...

Claims

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Application Information

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IPC IPC(8): G06F21/52
CPCG06F21/52
Inventor 舒辉杜三彭小详康绯熊小兵祝跃飞张泉林昊
Owner THE PLA INFORMATION ENG UNIV
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