Semiconductor package and manufacturing method thereof
A semiconductor and passivation layer technology, applied in the fields of semiconductor/solid-state device manufacturing, semiconductor devices, semiconductor/solid-state device components, etc., and can solve problems such as the risk of damage to qualified chips
Inactive Publication Date: 2017-09-22
MICRON TECH INC
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However, this thermal curing process creates an increased risk of known-good-die loss
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[0032] The following detailed description refers to the content shown in the relevant drawings to illustrate the embodiments that can be implemented according to the present invention. These examples provide sufficient detail to enable those skilled in the art to fully understand and practice the present invention. Structural modifications can still be made and applied to other embodiments without departing from the scope of the present invention.
[0033] Therefore, the ensuing detailed description is not intended to limit the invention. The scope of the invention is defined by its claims. Those with equivalent meanings to the claims of the present invention shall also fall within the scope of the present invention.
[0034] The drawings referred to in the embodiments of the present invention are schematic diagrams and are not drawn to original scale, and the same or similar features are generally described with the same reference numerals. In this specification, "die", "s...
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The invention discloses a semiconductor package comprising a redistribution layer intermediary layer, having first and second sides. The redistribution layer intermediary layer comprises a first passivation layer, a dielectric layer, a metallic layer, a second passivation layer, and a plurality of solder pads, which are located in the first passivation layer. A semiconductor grain mounted on the first side of the redistribution layer intermediary layer. A molded plastic around a semiconductor grain. A solder mask covering the lower surface of the first passivation layer and exposing a plurality of solder ball pads through multiple openings in the solder mask. A metal layer under a bump is arranged at the bottom of each plurality of openings. A solder bump or tin ball is arranged on the metal layer under the bump at the bottom of each of the plurality of openings.
Description
technical field [0001] The invention relates to the technical field of semiconductor packaging, in particular to a wafer-level packaging and a manufacturing method thereof. Background technique [0002] The development of semiconductor technology is very fast, especially under the trend of miniaturization of semiconductor chips, the functions of semiconductor chips are required to be more diverse. That is to say, more output / input (I / O) pads are bound to be squeezed into a smaller area on the semiconductor chip, which makes the density of the bonding pads on the semiconductor chip increase rapidly, causing the packaging of the semiconductor chip to become more difficult. [0003] As is well known in the art, wafer level packaging (WLP) is wafer level packaging before the dies are diced and separated. Wafer-level packaging technology has certain advantages, such as shorter production cycle times and lower costs. Fan-out wafer-level packaging (FOWLP) is a packaging technolo...
Claims
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IPC IPC(8): H01L23/31H01L23/62H01L21/50H01L21/60H01L23/485
CPCH01L21/50H01L23/31H01L23/62H01L24/26H01L24/27H01L2224/26H01L2224/27H01L21/568H01L24/97H01L25/0655H01L25/18H01L25/50H01L2224/16227H01L2224/32225H01L2224/73204H01L2224/81005H01L2224/81815H01L2224/92125H01L2224/97H01L2924/15192H01L2924/15311H01L2924/18161H01L21/561H01L23/49816H01L23/5383H01L21/4857H01L2224/81H01L2224/83H01L2224/16225H01L2924/00H01L23/49805H01L23/49827H01L23/49822H01L21/78H01L2021/60255H01L24/19
Inventor 吴铁将施信益
Owner MICRON TECH INC