Method and system for scheduling instructions in a computer processor

Abstract

Supplementary instruction scheduling can be used in some cases in parallel fragment processors to schedule additional instructions, called supplementary instructions, to the supplementary instruction ports of execution fragments, and to use one or more execution fragment's main instruction ports for such Complementary instructions supply one or more operands. Furthermore, in some cases, instead of additional instruction scheduling or in addition to supplementary instruction scheduling, selective fragment partitioning can also be used in parallel fragment processors to selectively Divide groups of execution fragments.

Description

Background technique [0001] The present invention relates generally to data processing, and in particular to scheduling instructions in computer processors. [0002] As semiconductor technology continues to move closer to practical limits in increasing clock speeds, architects are increasingly focusing on parallelization in processor architectures for performance gains. At the chip level, multiple processor cores are usually placed on the same chip, working in much the same way as separate processor chips, or, to some extent, a completely separate computer . Furthermore, even within a core, parallelization is employed through the use of multiple execution units dedicated to processing certain types of operations. Pipelining is also employed in many cases so that certain operations that may take multiple clock cycles to execute are divided into multiple stages, enabling other operations to start before earlier operations complete. Multithreading is also employed so that mult...

AI Technical Summary

Problems solved by technology

However, resources may still be bound to busy pipelines, and when all pipeline(s) assigned to an instruction stream are busy, the instruction stream may become stalled, reducing the potential throughput of the processor core

Images