Chip package structure

Abstract

A chip package structure is provided. The chip package structure includes a substrate. The chip package structure includes a chip package stacked over the substrate. The chip package structure includes first conductive bumps arranged between and in direct contact with the chip package and the substrate providing a clearance. The chip package structure includes a chip structure having a first face and an opposing second face arranged in the clearance between the chip package and the substrate and adjacent to the first conductive bumps. The chip structure contains at least one chip. The chip package structure includes a solder cap connecting the first face of the chip structure and the chip package. The chip package structure includes a second conductive bump connecting the second face of the chip structure and the substrate.

Description

technical field [0001] Embodiments of the present disclosure relate to chip packaging structures. Background technique [0002] The semiconductor integrated circuit industry has experienced rapid growth. Technological advances in integrated circuit materials and design have produced generation after generation of integrated circuits. Each generation of integrated circuits has smaller and more complex circuits than the previous generation. However, these advances also increase the complexity of the integrated circuit process. [0003] In integrated circuit innovation, functional density (the number of interconnect devices per unit area) increases, while geometric size (eg, the smallest component or circuit that can be formed by a process) shrinks. The shrinking process described above is generally beneficial for increasing production capacity and reducing associated costs. [0004] However, the continuous shrinking of the structure size makes the process more and more dif...

AI Technical Summary

Problems solved by technology

[0004] However, the continuous shrinking of the structure size makes the process more and more difficult to implement

Images