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High-voltage PMOS transistor in low-voltage process

A transistor and process technology, applied in the field of semiconductor integrated circuits, can solve the problems of high chip cost and long output time.

Inactive Publication Date: 2017-11-17
长沙方星腾电子科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] In order to solve the technical problems of high chip cost and long production time caused by the existing high-voltage process, the present invention provides a high-voltage PMOS transistor in a low-voltage process

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  • High-voltage PMOS transistor in low-voltage process

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Embodiment Construction

[0008] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in combination with specific embodiments and with reference to the accompanying drawings. It should be understood that these descriptions are exemplary only, and are not intended to limit the scope of the present invention. Also, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concept of the present invention.

[0009] In order to solve the technical problems of high chip cost and long production time caused by the existing high-voltage process, the invention provides a high-voltage PMOS transistor in the low-voltage process. Such as figure 1 As shown, including: P-type substrate PSUB, N-type well NWELL, P-type well PWELL, first P-type doping P+1, second P-type doping P+2 and polysilicon POLY; P-type substrate PSUB is located A...

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Abstract

The invention provides a high-voltage PMOS transistor in a low-voltage process, and belongs to the technical field of a semiconductor integrated circuit. The transistor comprises a P type substrate PSUB, an N type well NWELL, a P type well PWELL, a first P type doped P+1, a second P type doped P+2 and polysilicon POLY. On the basis of the conventional low-voltage PMOS transistor, the P type well PWELL is added to the periphery of the second P type doped P+2, so that the second P type doped P+2 can be not in direct contact with the N type well NWELL; and by virtue of the doping characteristic of a diode, the reverse breakdown voltage of a parasitic PN junction diode formed by the second P type doped P+2 and the N type well NWELL is far lower than that of a parasitic PN junction diode formed by the P type well PWELL and the N type well NWELL, so that the drain D of the device can bear a higher voltage compared with the drain of a low-voltage device, and application requirements of many high-voltage occasions can be satisfied.

Description

technical field [0001] The invention belongs to the technical field of semiconductor integrated circuits, and in particular relates to a high-voltage PMOS transistor in a low-voltage process. Background technique [0002] At present, in products such as power management chips, in order to save area, the digital circuit part often needs to use low-voltage devices, and in order to better withstand voltage, the analog circuit part needs to use high-voltage devices. Therefore, on many chips, high-voltage devices and low-voltage devices need to be integrated at the same time. [0003] In order to cope with this trend, the current traditional approach is to introduce a high-pressure process on the basis of a low-pressure process. The high-voltage process needs to increase the high-voltage P-type injection layer, N-type injection layer, high-voltage P-well, high-voltage N-well and other multi-layer masks on the basis of the low-voltage process, which greatly increases the cost of ...

Claims

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Application Information

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IPC IPC(8): H01L29/06H01L29/772
CPCH01L29/0615H01L29/772
Inventor 不公告发明人
Owner 长沙方星腾电子科技有限公司