Arbitrary frequency dividing ratio clock generation circuit
A technology of clock generation circuit and frequency division ratio, applied in the direction of electric pulse generator circuit, differential amplifier to generate pulses, etc., can solve the problem of high hardware cost of clock generator
Pending Publication Date: 2017-11-24
SHANGHAI EASTSOFT MICROELECTRONICS
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Problems solved by technology
[0003] In the prior art, to meet the requirements of clock signals of different frequencies, it is necessary to set up clock generation circuits corresponding to frequency division ratios respectively, resulting in a large hardware overhead of the clock generator
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[0024] In some circuitry, there may be a need to divide the time base by a non-integer frequency. In the prior art, a phase-locked loop circuit may be used to implement non-integer frequency division of the time base. However, the existing time-base non-integer frequency division circuit has large hardware overhead and is easily affected by the environment. If an additional oscillator is directly used to generate a required clock signal, it will also face the problem of high hardware overhead.
[0025] In the embodiment of the present invention, the first charge storage is charged and discharged monotonously and linearly with a preset period, so that the level of the output signal of the comparator jumps periodically, thereby realizing the frequency division processing of the original clock signal. By setting the capacitance value of the first charge storage device with a preset target frequency division ratio N, the original clock signal can be divided by N. Compared with us...
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An arbitrary frequency dividing ratio clock generation circuit comprises a voltage control circuit, a first charge storage, a comparator and a first switching circuit, wherein the voltage control circuit is arranged between a first voltage source and the first charge storage; a first end of the first charge storage is coupled with a first input end of the comparator, and potential of a second end of the first charge storage is first potential; a second input end of the comparator is coupled with a second voltage source, an output end is coupled with a control end of the first switching circuit, and an output signal of the comparator is a comparison result between an output voltage of the second voltage source and a first end voltage of the first charge storage; and a first end of the first switching circuit is coupled with the first end of the first charge storage, potential of a second end of the first switching circuit is first potential, and the first switching circuit is suitable to be conducted when the comparison result is that the first end voltage of the first charge storage reaches the output voltage of the second voltage source. By adopting the scheme, the hardware overhead of the arbitrary frequency dividing ratio clock generation circuit can be effectively reduced.
Description
technical field [0001] The invention relates to the field of circuits, in particular to a clock generation circuit with an arbitrary frequency division ratio. Background technique [0002] In most electronic systems, a clock generator circuit is required to provide a clock signal. The frequencies of clock signals required by different circuit modules may be different. In order to facilitate synchronous operation, the clock signals used by different circuit modules are provided by the same time base, and the same time base is divided to generate clock signals of different frequencies and provided to different circuit modules. In some circuit systems, there may be a demand for non-integer frequency division of the time base, and a phase-locked loop circuit is usually used to implement non-integer frequency division of the time base. [0003] In the prior art, to meet the requirements of clock signals of different frequencies, clock generation circuits corresponding to freque...
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Login to View More IPC IPC(8): H03K3/023
CPCH03K3/023
Inventor 关硕陈光胜
Owner SHANGHAI EASTSOFT MICROELECTRONICS