Shallow trench isolation structure and manufacture method for the same
A manufacturing method and technology of isolation structure, which are applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve problems such as device failure, reduce electron mobility, and threshold voltage instability, reduce compressive stress, and increase electron migration. rate, the effect of improving performance
Inactive Publication Date: 2017-11-28
SEMICON MFG INT (SHANGHAI) CORP +1
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[0003] During the thermal annealing process after filling the isolation oxide, the thermal mismatch between the substrate and the isolation oxide layer will generate compressive stress at the interface, reduce electron mobili
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Abstract
The invention provides a shallow trench isolation structure and a manufacture method for the same. The manufacture method for the shallow trench isolation structure comprises steps of providing a semiconductor substrate, forming a shallow trench in the semiconductor substrate, forming a liner oxide layer on side walls and a bottom of the shallow trench, performing ion injection to perform doping on the liner oxide layer, and filling isolation oxide in the shallow trench in order to form a shallow trench isolation structure. The manufacture method for the same can reduce a pressure stress of the isolation oxide of the shallow trench isolation structure and can inhibit dopant like boron from diffusing into the isolation oxide.
Description
technical field [0001] The invention relates to the technical field of semiconductors, in particular to a shallow trench isolation structure and a manufacturing method thereof. Background technique [0002] With the rapid development of semiconductor technology, the integrated circuit manufacturing process has entered the deep submicron era. Shallow trench isolation (Shallow Trench Isolation, STI) technology has become a device isolation technology widely used in the manufacturing process of CMOS devices due to its excellent isolation performance and flat surface shape. As the device size drops below 65 nanometers, the isolation oxide filling process for shallow trenches has higher requirements, and the isolation oxide filling process has developed from a high density plasma (High Density Plasma, HDP) process to a high aspect ratio (High Aspect Ratio Process, HARP) process. [0003] During the thermal annealing process after filling the isolation oxide, the thermal mismatc...
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Login to View More IPC IPC(8): H01L21/762
CPCH01L21/76237
Inventor 孙凌
Owner SEMICON MFG INT (SHANGHAI) CORP
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