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Chip package and method of forming a chip package

A chip packaging and chip technology, applied in the field of forming chip packages, can solve problems such as limited shelf life

Active Publication Date: 2017-11-28
INFINEON TECH AG
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, it has a very limited shelf life and strict rules may apply in the assembly plant (e.g. shipping in a sealed package with an inert medium, limited use time once the sealed package is opened, etc.)

Method used

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  • Chip package and method of forming a chip package
  • Chip package and method of forming a chip package
  • Chip package and method of forming a chip package

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Embodiment Construction

[0029] The following detailed description refers to the accompanying drawings, which show, by way of illustration, specific details and embodiments in which the invention can be practiced.

[0030] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment or design described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments or designs.

[0031] The term "over" as used in reference to deposited material formed "on" a side or surface can be used herein to mean that the deposited material can be directly—eg, in direct contact—on said "side" or "surface" formed above. The term "over" as used in reference to a deposition material formed "on" a side or surface can be used herein to mean that the deposition material may be formed indirectly on said side or surface such that one or more additional layers Arranged between said side or surface and the deposition material.

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PUM

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Abstract

In various embodiments, a chip package is provided. The chip package may include a chip including a chip metal surface, a metal contact structure electrically contacting the chip metal surface, and packaging material including a contact layer being in physical contact with the chip metal surface and / or with the metal contact structure; wherein at least in the contact layer of the packaging material, a summed concentration of chemically reactive sulfur, chemically reactive selenium and chemically reactive tellurium is less than 10 atomic parts per million.

Description

technical field [0001] Various embodiments relate generally to a chip package and a method of forming the chip package. Background technique [0002] A chip package may generally include a chip, a metal contact structure in electrical contact with the chip, and an encapsulation material at least partially surrounding the chip and the metal contact structure. The metal contact structure may provide an electrically conductive connection to the chip from outside the encapsulation material. The metal contact structure may include a bond wire, which may include or consist of copper (Cu). Bond wires made of bare copper material can have a significant cost advantage over gold (Au) wire, which has been and still is the dominant wire material used. However, copper wire can have some technical disadvantages and deficiencies, which hinder its rapid use and degree of industrial acceptance. For example, copper is readily oxidized in ambient air. Therefore, its shelf life is very limi...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/29H01L21/56
CPCH01L21/56H01L23/295H01L2924/181H01L24/29H01L24/32H01L24/45H01L24/73H01L2224/2919H01L2224/32245H01L2224/45139H01L2224/45147H01L2224/45565H01L2224/45572H01L2224/48247H01L2224/48465H01L2224/73265H01L23/3107H01L23/3142H01L23/49582H01L23/293H01L24/48H01L2924/00012H01L2924/00014H01L2924/01046H01L2224/45664H01L2224/45644H01L2224/45669H01L2924/00H01L23/296H01L2224/48647H01L2924/01029H01L2924/365
Inventor M·鲍尔R·恩格尔M·许廷格W·卡纳特H·克尔纳J·马勒B·吕勒
Owner INFINEON TECH AG