Via contact using silicide

Abstract

The present invention relates to via contacts using silicide, which provides a method of forming a silicide layer as a via contact under a gate contact between a p-epitaxial layer and an n-epitaxial layer source / drain and an apparatus for its production . Specific embodiments include depositing a semiconductor layer over a substrate; forming a pFET gate on the p-side of the semiconductor layer and an nFET gate on the n-side of the semiconductor layer; between the pFET gate and the nFET gate form a gate contact between the pFET and nFET gates; form a raised source / drain on opposite sides of each of the pFET and nFET gates; and form a raised source / drain over the first raised source / drain on the p-side and a second raised Metal silicide over raised source / drain, wherein the metal silicide is from the first raised source / drain to the second raised source / drain and the gate between the pFET and nFET gates The contact portion extends below.

Description

technical field [0001] The present invention relates to semiconductor layout. In particular, the invention relates to via contacts between p- and n-epitaxial layers in semiconductor devices. Background technique [0002] Existing standard cell library configurations provide competitive cell areas and densities. Among those cell bank constructions used in more advanced technology nodes are via contacts. As technology continues to produce smaller semiconductor devices, the spacing between middle-of-line (MOL) layers is also shrinking. This leads to metal 1 (M1) to gate contact (CB) spacing in technologies such as fully depleted silicon-on-insulator (FD-SOI), 20 low power mobile (LPM ) source / drain contact (CA) to CB space for computing applications, or trench silicide (trench silicide; TS) to CB space for 20 LPM computing applications, etc. MOL and back-end process (back-end- of-the-line; BEOL) layers appear crowded. In addition, other design rules such as CB to gate (PC)...

AI Technical Summary

Problems solved by technology

results in a crowded cluster library design for M1, which limits the lateral flipping of cells

Also M1 jogs are required, which introduces rounded corners, and also causes M1 to be crowded

Furthermore, for 20 LPM operation applications, using a CB offset that reduces the CB-PC contact area, and there is a risk of CB-PC opening, which results in a high-risk configuration

Images