A kind of multifunctional clock buffer suitable for sram type fpga

Abstract

The invention relates to a multifunctional clock buffer suitable for an SRAM type FPGA. The buffer comprises a first clock control circuit B101, a second clock control circuit B102 and an output multiplexer B103; the clock buffer disclosed by the invention is used for driving a global clock network in the FPGA; different working modes are realized according to FPGA configuration; the first working mode is an ordinary clock buffer; the second working mode is an enabled clock buffer; when the clock buffer is not enabled, the output clock is fixed at high level; the third working mode is a clock multiplexer capable of completing burr-free switching of two clocks; the fourth working mode is an enabled clock multiplexer capable of completing burr-free switching of two clocks; and, when the clock multiplexer is not enabled, the output clock is fixed at high level. A buffer circuit additionally provides an input clock slighting control port; and thus, switching operation of a clock can be completed under a condition that the clock is disappeared.

Description

technical field [0001] The invention relates to a multifunctional clock buffer suitable for SRAM type FPGA, which belongs to the technical field of integrated circuits. Background technique [0002] A Field Programmable Logic Gate Array (hereinafter referred to as FPGA) can implement different logic functions according to configuration information. The SRAM type FPGA uses a configuration memory array composed of SRAM units to store user configuration information. The configuration frame composed of SRAM units can be programmed repeatedly indefinitely, making the FPGA application very flexible, especially suitable for aerospace engineering. The characteristic requirements of high reliability, multiple varieties, and small batches of devices are widely used in aerospace engineering. [0003] With the increase of the complexity of the digital system, the system has higher and higher requirements for the clock. The global clock network inside the FPGA can provide high-quality c...

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Problems solved by technology

[0003] With the increase of the complexity of the digital system, the system has higher and higher requirements for the clock. The global clock network inside the FPGA can provide high-quality clocks for the whole chip, but it needs a driving circuit for the global clock network, which has not yet been seen. to the corresponding public information

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