Threshold voltage and well implantation method for semiconductor devices
A semiconductor and fin technology, used in patterning and ion implantation technology, lithography and ion implantation fields
Active Publication Date: 2020-10-13
GLOBALFOUNDRIES U S INC MALTA
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- Application Information
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Problems solved by technology
Topography effects, boolean comps and etch bias may have further negative effects on patterning margins with narrow N-P junction spacing
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[0056] In the following description, for purposes of explanation, numerous specific details are set forth to provide a thorough understanding of exemplary embodiments. It is evident, however, that the exemplary embodiments may be practiced without these specific details or with an equivalent arrangement. In other instances, well-known structures and devices are shown in block diagrams in order to avoid unnecessarily obscuring illustrative embodiments. Furthermore, all numbers expressing quantities, ratios and numerical properties of ingredients, reaction states, etc. in this patent specification and claims are to be understood as being modified in all instances by the word "about" unless otherwise presented.
[0057] This disclosure addresses and addresses current issues requiring expensive immersion plating with minimum area requirements for critical gate pitch, narrow N-P junction collapse process margins, and critical CRR for semiconductor processing prevalent in sub-10nm t...
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The present invention relates to a threshold voltage and a well implantation method for a semiconductor device. The method for patterning and implantation provides multiple specific embodiments, including the following steps: forming a plurality of fins; forming a SiN on the plurality of over the fin; forming an a-Si layer over the SiN; forming and patterning a first patterned layer over the a-Si layer; using the first patterned layer as a mask, etching through the a -Si layer; removing the first patterned layer; implanting ions in exposed fin groups; forming and patterning a second patterned layer to expose a first fin group and the a-Si layer On a portion of two opposite sides of the first fin group; implanting ions in a first region of the first fin group; forming a third patterned layer on the first fin group over the first region and exposing a second region of the first fin group; and implanting ions in the second region of the first fin group.
Description
technical field [0001] The present disclosure relates to photolithography and ion implantation of semiconductor devices. In particular, the disclosure relates to patterning and ion implantation techniques for semiconductor devices having fins at the sub-10 nanometer (nm) technology node. Background technique [0002] As semiconductor processing advances to the 10nm technology node, numerous technical challenges force the use of more expensive immersion layers. Some technical challenges include the minimum area requirement for the critical gate pitch (3CPP), the narrower N-P junction collapse process margin at the 10nm technology node, and the more critical corner fillet at the 10nm technology node Requirements (corner rounding requirement; CRR). Due to these technical challenges, an immersion plating process for multiple layers becomes necessary. With current processing at the 10nm technology node, there is a significant reduction in process margin due to the effect of ed...
Claims
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IPC IPC(8): H01L21/033
CPCH01L21/0334H01L21/823814H01L21/266H01L21/823821H01L21/26513H01L27/0924H01L21/3083H01L21/02118H01L21/0276H01L21/02238H01L29/66803H01L21/31155H01L21/0271H01L21/3065H01L21/76213H01L21/76224H01L21/02255H01L27/0207H01L29/66795H01L21/26506
Inventor 戴鑫托布莱恩·葛伦马翰德·库玛丹尼尔·J·德契恩丹尼尔·杰格
Owner GLOBALFOUNDRIES U S INC MALTA