CMOS device and fabrication method thereof

Abstract

The invention provides a CMOS device and a fabrication method thereof. The method comprises steps: a semiconductor substrate is provided; a first blocking layer is formed on the surface of the semiconductor substrate; hydrogen or oxygen plasma passivation processing is carried out on the first blocking layer on a second N channel area and a second P channel area; a first work function layer is formed on the first blocking layer on a first P channel area and the second P channel area; a second work function layer is formed on the first blocking layer on a first N channel area and the second N channel area and the first work function layer; and/or hydrogen or oxygen plasma passivation processing is carried out on the first blocking layer on the second N channel area and the first work function layer on the second P channel area. The method is high in threshold adjustment control precision, the process flexibility is high, and the method is simple and easy to operate and is more suitable for multi-threshold regulation on a small-size device.

Description

technical field [0001] The present invention relates to the technical field of semiconductor device manufacturing, and more specifically, to a CMOS (Complementary Metal Oxide Semiconductor, Complementary Metal Oxide Semiconductor) device and a manufacturing method thereof. Background technique [0002] As the integration level of integrated circuits continues to increase, the size of devices continues to decrease. It is difficult for traditional planar CMOS (Complementary Metal Oxide Semiconductor) devices to continue to reduce the key dimensions. Three-dimensional devices such as FINFET (Fin Field Effect Transistor) and Nanowire channel devices are gradually becoming the mainstream trend. [0003] After entering the nanometer node, the adjustment of the threshold voltage of CMOS devices has always been an important and difficult point in the manufacture of semiconductor devices. At present, it is mainly adjusted by adjusting ion implantation, gate length, gate dielectric la...

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Problems solved by technology

[0003] After entering the nanometer node, the adjustment of the threshold voltage of CMOS devices has always been an important and difficult point in the manufacture of semiconductor devices. At present, it is mainly adjusted by adjusting ion implantation, gate length, gate dielectric layer thickness and work function layer thickness. The threshold voltage of semiconductor devices, and with the further reduction in the size of semiconductor devices, especially when entering below the 10nm node, multiple threshold voltages need to be adjusted, but due to the space constraints and parasitic effects brought about by the size reduction, Higher requirements are put forward for the threshold adjustment of CMOS devices, and these traditional methods can no longer achieve multi-threshold adjustment well.

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