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ATE multiple-time-domain testing device

A test device and time-domain technology applied in the field of ATE multi-time-domain test devices to achieve the effect of saving memory and meeting the requirements of concurrent testing

Inactive Publication Date: 2017-12-29
SINO IC TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] The present invention proposes an ATE multi-time-domain test device, which can remove the limitation of the existing ATE system on multi-time-domain test requirements, improve test efficiency, and better adapt to the requirements of more and more complex chips for testing.

Method used

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Embodiment Construction

[0016] The specific embodiments of the present invention are given below in conjunction with the accompanying drawings, but the present invention is not limited to the following embodiments. Advantages and features of the present invention will be apparent from the following description and claims. It should be noted that all the drawings are in very simplified form and use imprecise ratios, which are only used for the purpose of conveniently and clearly assisting in describing the embodiments of the present invention.

[0017] Please refer to figure 2 , figure 2 Shown is a schematic structural diagram of an ATE multi-time-domain testing device in a preferred embodiment of the present invention. The present invention proposes a kind of ATE multi-time domain test device, comprising:

[0018] A system clock generator 100, configured to generate a system clock signal;

[0019] A plurality of test channels 200, each test channel 200 is respectively provided with an adjustabl...

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Abstract

The invention provides an ATE multiple-time-domain testing device which comprises the components of a system clock generator which is used for generating a system clock signal; and a plurality of testing channels, wherein each testing channel is provided with a phase-locked loop with adjustable frequency. Each phase-locked loop with adjustable frequency is connected with a system clock generator. The independent clock signal of each testing channel is generated through frequency modulation processing. According to the ATE multiple-time-domain testing device provided by the invention, a mode of distributing one clock to all testing channels in an existing ATE testing system is changed. Each channel is provided with an independent clock, and a plurality of clock systems can be generated accordingly, thereby more flexibly generating required testing vectors with multiple frequencies, well satisfying a concurrent testing requirement of a chip, realizing no requirement for vector configuration again, greatly saving a testing vector memory, and realizing no requirement for adding of a complicated external module on a DUT board.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuit testing, and in particular to an ATE multi-time domain testing device. Background technique [0002] In integrated circuit testing, some complex devices require different internal modules to work in different clock domains at the same time. In addition, with the rapid development of integrated circuits, the integration of chips is getting higher and higher, and there are more and more integrated modules. It takes a lot of time to cover each module during the test process. At this time, the requirement of concurrent testing is put forward. That is, multiple modules are tested at the same time to save test time, and the frequency requirements of each module are different, which also requires our ATE to be able to perform multi-time domain tests. ATE is an automatic test equipment used in integrated circuit testing. However, most ATEs currently only have one system clock, that is, th...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G01R31/28
Inventor 邓维维张志勇王华王锦凌俭波
Owner SINO IC TECH
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