Overlay error measurement and problem assessment method

Abstract

The invention provides an overlay error measurement and problem assessment method. The method comprises the steps of inputting an overlay error measurement solution; inputting all overlay error measurement identification information; inputting a target upper limit and a target lower limit and an overlay error exception assessment standard; finishing data collection, comparing a measurement value with the upper limit and the lower limit, and marking excess data points as problem points; determining whether to increase a new data collection solution according to the assessment standard, if a proportion of problem points exceeds a preset value, generating an overlay error exception report; and if the proportion of problem points are within the preset value, determining, according to the assessment standard, which measurement identifiers are to be included into the new data collection solution for measurement; and if newly obtained measurement data has problem points, marking the problem points till all measurement data of overlay errors are within the target upper limit and the target lower limit, and generating an overlay error problem and problem impact degree report. The method canshorten the time determining the range of the overlay error problems, and obtains overlay error problems and a problem impact degree, so as to enable an engineer to determine and take a process solution of next step.

Description

technical field [0001] The invention relates to the field of microelectronic photolithography technology, and in particular to an intelligent overlay error measurement and problem assessment method. Background technique [0002] The pattern (current layer) remaining on the photoresist after exposure and development must be aligned with the existing pattern (front layer) on the wafer substrate, so as to ensure correct connection between various parts of the device. Too much alignment error is one of the main causes of device short circuit and open circuit, which greatly affects the yield of the device. In the process of integrated circuit manufacturing, there is special equipment to determine the overlay error (overlay) by measuring the relative position between the current layer pattern and the previous layer pattern on the wafer. The graphics on the wafer specially used to measure the overlay error are overlay marks, which have been placed in the designated area when desig...

AI Technical Summary

Problems solved by technology

The problem with this general method is that it takes a long time to establish a new measurement solution after the problem is found, which increases the time for loading and unloading wafers, affects production capacity, and abnormal points may appear in any position , Artificially judging the problem area is easy to cause omissions

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