A Comparator Applied to High Speed ​​Pipeline ADC

Abstract

The invention discloses a comparator for high-speed pipelined ADCs, which includes a switched capacitor sampling front-end circuit, a pre-amplification circuit, and a capacitor storage latch output circuit. The switched capacitor sampling front-end circuit samples and inputs an input signal and a reference voltage. The pre-amplification circuit pre-amplifies the sampled input signal. As the pre-amplification circuit is not directly connected with the output of rail-to-rail voltage change, the kickback noise can be reduced to a certain extent. The cross coupled structure adopted in the pre-amplification level can also reduce the influence of kickback noise. The capacitor storage latch output circuit uses two phase inverters connected end to end to constitute a positive feedback loop, in order to amplify, latch and output a small comparison result stored in a capacitor. Two NMOS tubes MN3 and MN4 in the level are turned off when rail-to-rail voltage change is produced in the comparator regeneration stage, in order to isolate the input end from the rail-to-rail output change. Therefore, the influence of kickback noise is greatly eliminated.

Description

technical field [0001] The invention relates to the field of CMOS integrated circuit design, in particular to the design of a comparator. Background technique [0002] With the wide application of integrated circuit chips, digital communication has also received more and more attention. As a key module for converting analog signals into digital signals, more and more designers are constantly optimizing and innovating. field. Among different types of ADCs, the pipeline ADC gradually stands out from many types because of its high speed, high precision, and low power consumption. As a performance module for realizing high-speed pipeline ADC, the comparator is essential for its high-performance design. [0003] Comparators mainly include A-B type latch comparators and dynamic comparators. The A-B type latch comparator has higher precision and less kickback noise, but it is slower and has static power consumption; the dynamic comparator is faster and has lower power consumptio...

AI Technical Summary

Problems solved by technology

[0004] Aiming at the design requirements of low power consumption and high-speed pipeline ADC, the present invention adopts a dynamic comparator, and provides a high-speed comparator that can greatly control the influence of kickback noise for the disadvantage of relatively large kickback noise in the prior art. Comparator for pipelined ADC

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