A Static Huffman Parallel Full Coding Implementation Method

Abstract

A static state Huffman parallel full coding realization method comprises the following steps: ranking so as to obtain a code length and a coding value matched with a weight, coding all variables in aclock period, and obtaining code lengths and coding values of all variables when the ranking is over; the method fully considers the FPGA parallel processing property in the whole process, and uses anoptimized parallel full comparison algorithm to obtain the ranking of all variable weights in only one clock period; the algorithm is realized by parallel comparison of two random numbers in the sequence; a more than or equal to comparator is uniformly employed to compare every two data items; two random numbers only need to be compared for one time, the obtained comparison result contains mutualopposite numbers. A module firstly inputs data and records weight values; when the input is over, the inputted data is optimized, and parallel full comparison ranking is carried out, thus obtaining the ranking result while coding the inputted data; finally, the coding value is outputted in a streamline mode, so the output process is not interrupted.

Description

technical field [0001] The invention relates to FPGA and data and image compression technology, in particular to a static Huffman parallel full encoding method based on FPGA. Background technique [0002] Since 1952, when David A. Huffman was studying for a doctorate at MIT, he proposed to construct the codeword with the shortest average length of different prefixes based on the probability of character appearance, which can be called the best encoding, generally known as static Huffman encoding. The steps are to gradually construct a static Huffman tree by comparing weights, and then encode and decode the static Huffman tree. Generally, static Huffman encoding needs to build a static Huffman tree, and then encode one by one from the root to the leaves. Such encoding efficiency is not only very low, but also requires more hardware resources, and the obtained clock frequency is not high. [0003] In order to achieve a higher clock frequency with less hardware resources, a ne...

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Problems solved by technology

[0004] The present invention aims at the problems that the coding cycle is not fixed in static Huffman coding, the coding efficiency is not high, the utilization rate of hardware resources needs to be reduced and the highest clock frequency needs to be improved, etc., and a static Huffman parallel full coding method based on FPGA is proposed. This method is fully utilized The parallelism and pipeline technology of FPGA can get the coding value while sorting the weights, and no matter how the weights of the input variables change, the whole coding process only needs a fixed clock cycle

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