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Noise reduction edge detection method based on FPGA

An edge detection and noise reduction technology, applied in image data processing, instrumentation, computing, etc., can solve problems such as image noise cannot be well filtered, and achieve the effect of improving operating efficiency and improving clarity

Inactive Publication Date: 2018-01-26
TIANJIN UNIVERSITY OF TECHNOLOGY
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Problems solved by technology

[0002] Edge detection is an important part in the field of digital image processing. The traditional edge detection operator uses drastic changes in grayscale to detect the edge of the image. Although these methods can detect the edge, they are not very good for the noise in the image. Good filtering produces larger response

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  • Noise reduction edge detection method based on FPGA
  • Noise reduction edge detection method based on FPGA
  • Noise reduction edge detection method based on FPGA

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Embodiment Construction

[0024] The present invention will be described below in conjunction with the accompanying drawings and examples.

[0025] figure 1 It is the general design block diagram of the system adopted by the present invention, and what the core FPGA chip adopts is Cyclone IV EP4CE115F29C7N of Altera Company. The algorithm processing module programs the noise reduction edge detection algorithm through Verilog language, compiles and synthesizes it with quartusII software, and downloads it to the chip to form a corresponding hardware circuit; the hardware circuit diagram of the picture storage module is as follows: figure 2 As shown, first, use the mapping software to convert a picture into two mif format files that can be recognized by the FPGA, and store them in the two single-port ROM IP cores in the FPGA. In order to save chip resources, one of the mif files is the pixel of the picture Index value, another mif file is the pixel value corresponding to the index value, output 24-bit t...

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Abstract

The invention relates to a noise reduction edge detection method based on FPGA. The method comprises steps that a to-be-processed image is converted into an mif format file which is saved into a single-port ROM IP core of the FPGA, and the image data is read from an ROM through utilizing address counting; convolution operation of the image and a 5*5 Gaussian Laplace operator is carried out; templates of four-direction sobel operators are utilized to calculate a maximum first-order partial derivative of a center point of a 7*7 array in four directions; LOG operator convolution value thresholding is carried out, and a suspected zero crossing point and a nonzero crossing point are found out; for the suspected zero crossing point, the suspected zero crossing point is considered to be a real zero crossing point when the suspected zero crossing point is consistent with a gradient normal direction of the center point, if not, the suspected zero crossing point is considered to be a fake zero crossing point; for the real zero crossing point and the fake zero crossing point, expansion and corrosion operation in the gradient direction is respectively carried out; for the non-zero crossing point, corrosion expansion open operation is carried out, image de-noising is carried out, and an edge of the image is acquired.

Description

technical field [0001] The invention relates to the technical fields of image processing and machine vision. Background technique [0002] Edge detection is an important part in the field of digital image processing. The traditional edge detection operator uses drastic changes in grayscale to detect the edge of the image. Although these methods can detect the edge, they are not very good for the noise in the image. Good filtering produces a larger response instead. How to improve the accuracy of edge detection is a problem that many scholars have been studying. Contents of the invention [0003] The object of the present invention is to provide a more accurate image edge detection effect that can achieve accurate edge detection even for pictures polluted by noise. Moreover, the advantages of FPGA parallelism and pipeline processing are used to improve the real-time and portability of the system. An FPGA-based noise reduction type edge detection system is provided. Tech...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06T7/13G06T7/136G06T5/00G06T5/30
Inventor 董恩增杜建宝佟吉刚张祖锋陈超焦迎杰
Owner TIANJIN UNIVERSITY OF TECHNOLOGY