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A Noise Reduction Edge Detection Method Based on FPGA

An edge detection and noise reduction technology, applied in the field of image processing and machine vision, can solve the problem that image noise cannot be well filtered, and achieve the effect of improving operating efficiency and improving clarity

Inactive Publication Date: 2021-03-02
TIANJIN UNIVERSITY OF TECHNOLOGY
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Problems solved by technology

[0002] Edge detection is an important part in the field of digital image processing. The traditional edge detection operator uses drastic changes in grayscale to detect the edge of the image. Although these methods can detect the edge, they are not very good for the noise in the image. Good filtering produces larger response

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  • A Noise Reduction Edge Detection Method Based on FPGA
  • A Noise Reduction Edge Detection Method Based on FPGA
  • A Noise Reduction Edge Detection Method Based on FPGA

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Embodiment Construction

[0024] The present invention will be described below in conjunction with the accompanying drawings and examples.

[0025] figure 1 It is the general design block diagram of the system adopted by the present invention, and what the core FPGA chip adopts is Cyclone IV EP4CE115F29C7N of Altera Company. The algorithm processing module programs the noise reduction edge detection algorithm through Verilog language, compiles and synthesizes it with quartusII software, and downloads it to the chip to form a corresponding hardware circuit; the hardware circuit diagram of the picture storage module is as follows: figure 2 As shown, first, use the mapping software to convert a picture into two mif format files that can be recognized by the FPGA, and store them in the two single-port ROM IP cores in the FPGA. In order to save chip resources, one of the mif files is the pixel of the picture Index value, another mif file is the pixel value corresponding to the index value, output 24-bit t...

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Abstract

The invention relates to an FPGA-based noise reduction edge detection method, comprising: converting an image to be processed into a mif format file, and storing it in a single-port ROM IP core in the FPGA, and using address counting to read image data from the ROM; Convolute the image with the 5×5 Gaussian Laplacian operator; use the template of the four-direction sobel operator to calculate the maximum first-order partial derivative in the four directions at the center point in the 7×7 array; LOG Threshold the operator convolution value to find suspicious zero-crossing points and non-zero-crossing points; for suspicious zero-crossing points, when it is consistent with the normal direction of the gradient at the center point, this point is considered to be a true zero-crossing point, otherwise it is False zero-crossing points; for true zero-crossing points and false zero-crossing points, dilation and erosion operations in the gradient direction are performed respectively; for non-zero crossing points, the opening operation of erosion and expansion is performed to denoise the image and obtain the edge of the image.

Description

technical field [0001] The invention relates to the technical fields of image processing and machine vision. Background technique [0002] Edge detection is an important part in the field of digital image processing. The traditional edge detection operator uses drastic changes in grayscale to detect the edge of the image. Although these methods can detect the edge, they are not very good for the noise in the image. Good filtering produces a larger response instead. How to improve the accuracy of edge detection is a problem that many scholars have been studying. Contents of the invention [0003] The object of the present invention is to provide a more accurate image edge detection effect that can achieve accurate edge detection even for pictures polluted by noise. Moreover, the advantages of FPGA parallelism and pipeline processing are used to improve the real-time and portability of the system. An FPGA-based noise reduction type edge detection system is provided. Tech...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06T7/13G06T7/136G06T5/00G06T5/30
Inventor 董恩增杜建宝佟吉刚张祖锋陈超焦迎杰
Owner TIANJIN UNIVERSITY OF TECHNOLOGY