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Microprocessor and execution method thereof

A microprocessor and processing core technology, applied in the direction of machine execution devices, data processing power supply, concurrent instruction execution, etc., can solve the problems of inability to provide speed, accuracy, system level transparency, etc., and achieve the effect of less power consumption

Active Publication Date: 2018-02-23
VIA TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This may be sufficient for many purposes, but may not provide otherwise desired speed, accuracy, and / or system-level transparency

Method used

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  • Microprocessor and execution method thereof
  • Microprocessor and execution method thereof
  • Microprocessor and execution method thereof

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Embodiment Construction

[0045] The following is an introduction to the preferred embodiments of the present invention. Each embodiment is used to illustrate the principle of the present invention, but not to limit the present invention. The scope of the present invention should be determined by the claims.

[0046] Please refer to figure 1 , which is a block diagram showing a multi-core microprocessor 100 . The microprocessor 100 includes a plurality of processing cores, denoted as 102A, 102B to 102N, which are collectively referred to as a plurality of processing cores 102, or a plurality of cores 102 for short, and are individually referred to as a processing core 102 or a core 102 for short. More preferably, each core 102 includes a pipeline of one or more functional units (not shown) including an instruction cache, an instruction translation unit or an instruction decoder, more preferably including A microcode unit, scratch renaming unit, reservation station, cache memory, execution unit, memo...

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Abstract

The invention provides a microprocessor and an execution method thereof. The microprocessor comprises a plurality of processing cores each of which instantiates the visible storage resources on the respective architectures. A first processing core of the above plurality of processing cores meets an architecture instruction, uses a value appointed by the above architecture instruction to indicate the first processing core to update the visible storage resources on the respective architectures of the first processing core. In order to respond to meet the above architecture instructions, the above first processing core provides the above numerical values to each of the above plurality of processing cores and uses the above values to update the visible storage resources on the respective architectures of the first processing core. Each of the processing core, except the first processing core uses the above value provided by the first processing core to update the visible storage resourceson the respective architectures of the first processing core on the condition of not meeting the above architecture instruction.

Description

[0001] This application is a divisional application of the application dated August 28, 2014, the application number is 201410431675.1, and the invention title is "Microprocessor and its execution method". technical field [0002] The present invention pertains to a microprocessor, and in particular to per-core real-time architecture visible storage update propagation. Background technique [0003] The increase in multi-core microprocessors is primarily due to the performance advantages they offer. This may be primarily due to the rapid reduction in the size of the geometric dimensions of semiconductor devices, thereby increasing transistor density. The existence of multiple cores in a microprocessor has created the need to communicate with one core and other cores to perform various functions such as power management, cache management, debugging, and configuration associated with more cores. [0004] Traditionally, programs (eg, operating systems or applications) running o...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/30G06F9/38G06F12/084G06F13/24G06F1/32
CPCG06F1/3203G06F1/3237G06F1/324G06F1/3287G06F1/3296G06F9/30079G06F9/30087G06F9/3885G06F12/084G06F13/24
Inventor G·葛兰·亨利史蒂芬·嘉斯金斯
Owner VIA TECH INC