Three-value static memory using word operation circuit and CNFET

Abstract

The invention discloses a three-value static memory using a word operation circuit and CNFET. The three-value static memory comprises a first P-type CNFET, a second P-type CNFET, a third P-type CNFET,a fourth P-type CNFET, a fifth P-type CNFET, a sixth P-type CNFET, a seventh P-type CNFET, an eighth P-type CNFET, a first N-type CNFET, a second N-type CNFET, a third N-type CNFET, a fourth N-type CNFET, a fifth N-type CNFET, a sixth N-type CNFET, a seventh N-type CNFET, an eighth N-type CNFET, a ninth N-type CNFET, a writing bit line, a reading bit line, a writing word line, an inverted writingword line, a reading word line and an inverted reading word line. The three-value static memory has low power consumption and can reduce time delay.

Description

technical field [0001] The invention relates to a three-valued static memory, in particular to a three-valued static memory utilizing word operation circuits and CNFETs. Background technique [0002] Traditional ternary SRAMs usually store data in the form of cross-coupled inverters. At present, the circuit diagrams of two kinds of ternary static memories designed by using CNFET tubes (that is, carbon nano field effect transistors) are as follows: figure 1 and figure 2 shown. [0003] figure 1 In the shown ternary static memory, a P-type CNFET (P1) and two N-type CNFETs (N1 and N2) constitute the first ternary inverter, and a P-type CNFET (P2) and two N-type The CNFET tubes (N3 and N4) form the second ternary inverter, and the first ternary inverter and the second ternary inverter form a pair of cross-coupled inverters; in the ternary static memory, The N-type CNFET tube N2 in the first three-value inverter is in a normally-on state, so when the circuit is working, whe...

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Problems solved by technology

[0004] figure 2 In the shown ternary static memory, 4 P-type CNFETs (P1, P2, P3, P4) and 2 N-type CNFETs (N1, N2) constitute the first ternary inverter, and 4 P-type CNFET tubes (P5, P6, P7, P8) and two N-type CNFET tubes (N3, N4) constitute the second ternary inverter, the first ternary inverter and the second ternary inverter Constitute a pair of cross-coupled inverters; in the three-valued static memory, when the input of the first three-valued inverter is a logic value "1", the P-type CNFET transistor P2 and the N-type CNFET transistor N3 are simultaneously turned on for voltage division The logic value "1" output is obtained. At this time, a DC path is formed between the power supply Vdd connected to the first three-value inverter and the ground, resulting in a large short-circuit current; the second three-value inverter also exists with the first three-value inverter. The same DC path problem of three ternary inverters, thus, when the ternary static memory stores logic value "1", there are two such DC paths, which increases the working power consumption of the circuit and makes the ternary static memory High memory power consumption

[0005] Moreover, the above two kinds of ternary static memories all implement data storage in the form of cross-coupled inverters. Since the output terminals of the two inverters are the input terminals of each other in the cross-coupled inverter, two inverters are required when writing data. The data writing can only be completed when all terminals reach the signal inversion condition, thus increasing the data writing delay

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