Refresh cycle adjustment method, DDR controller and DDR system

Abstract

The present application provides a refresh cycle adjustment method, a DDR controller, and a DDR system, in order to solve the bit error problem of some DDR particles at the end of life whose Data retention capability does not meet the DDR specifications due to aging. The method in embodiments of the present application comprises that: the DDR controller determines a specific memory cell of the DDRparticle, wherein the DDR particle comprises the a specific memory cell and a non-specific memory cell, and the data retention capacity of the specific memory cell is consistent with the data retention capability of the non-specific memory cell; the DDR controller carry out data retention capability on the specific memory cell according to a specific refresh cycle to obtain a specific scan result; and the DDR controller adjusts the refresh cycle of the non-specific memory cell according to the specific scan result.

Description

technical field [0001] The application relates to the field of computers, in particular to a method for adjusting a refresh period, a DDR controller and a DDR system. Background technique [0002] Each memory cell of Dynamic Random Access Memory (DRAM) uses a transistor (Transistor) and a capacitor (Capacitor). The capacitor is very small and easy to discharge very quickly. It needs to refresh the circuit to keep the charge, so as to keep stored information. [0003] The current common practice in the industry is to set a standard and fixed refresh cycle when the main chip starts, for example, a double-rate synchronous dynamic random access memory (Double Data Rate, DDR) has a fixed-value count row (Row count) in DDR particles. ), and the typical interval between refresh commands (Refresh) between lines, that is, tREFI (RefreshInterval), is 3.9us. In the interval sending mode, the interval between two adjacent refreshes of each row, tREFI*Rowcount, is fixed. [0004] Howe...

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Problems solved by technology

[0005] This application provides a refresh cycle adjustment method, a DDR controller and a DDR system, which are used to solve the bit error problem of some DDR particles whose Data retention capability does not meet the DDR specification due to aging at the end of life.

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