Method and device for extracting false paths in gate-level network lists, and terminal equipment

Abstract

The invention discloses a method and a device for extracting false paths in gate-level network lists, and terminal equipment. The method includes extracting all time sequence paths positioned among various clocks of different clock domains from the gate-level network lists; sorting and filtering the extracted time sequence paths according to screening conditions to obtain the false paths in the gate-level network lists. The screening conditions include that termination points of paths are time sequence devices, and clocks of the termination points do not include clocks of start points. The method, the device and the terminal equipment have the advantages that the false paths in the gate-level network lists can be quickly extracted by the aid of the method, accordingly, inspection and simulation verification can be carried out on the extracted false paths in SDC (Synopsys design constraint) cleaning phases, deficiency of SOC (system on a chip) designs can be checked, problems of the SOCdesigns further can be discovered at early phases, and the chip development efficiency can be greatly improved.

Description

technical field [0001] The invention relates to the field of system-on-chip (SOC) design, in particular to a method, device and terminal equipment for extracting false paths in gate-level netlists. Background technique [0002] In the system-on-chip (SOC) design process, its basic flow is the process from the system description, algorithm description to the abstract level of the function description, circuit description and production process level to the concrete level. [0003] Among them, after the system description, the algorithm description level and the conversion of the algorithm into an equivalent RTL (Register Transport Level, register conversion level circuit) description through the hardware description language, the next step is to carry out the digital logic circuit written in the hardware description language. Synthesized to generate a gate-level netlist. In this step, the mapping between the synthesizable register transfer level description and the synthesis...

AI Technical Summary

Problems solved by technology

[0006] The present invention provides a method, device and terminal equipment for extracting false paths in the gate-level netlist to solve the problem of chip design caused by the shortcomings of the existing false path search methods, such as long analysis time, cumbersome search, and easy omission. The problem of extended production cycle

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