Extensible reconfigurable multi-core processor connection method

Abstract

The invention discloses an extensible reconfigurable multi-core processor connection method. The method comprises the steps that S1, a reconfigurable on-chip resource array is established; S2, a reconfigurable multi-core network-on-chip is established; S3, on-chip routers are configured at intersections of connecting lines of the network-on-chip; and S4, programmable logic blocks are connected tothe on-chip routers. The technical scheme has high efficiency and flexibility, the network-on-chip and the reconfigurable technology are combined, all the programmable logic blocks are connected through the on-chip routers, therefore, connection on a chip is realized not through a bus but through the network-on-chip, wiring width is reduced, the utilization area of the chip is enlarged, and the extensible on-chip connection method is provided.

Description

technical field [0001] The invention relates to an expandable and reconfigurable multi-core processor connection method, which belongs to the technical field of reconfigurability. Background technique [0002] Reconfigurable computing is regarded as an effective solution that can combine the high flexibility of traditional processors with the high processing efficiency of ASIC (Application Specific Integrated Circuit). Due to the good adaptability of the reconfigurable architecture, the processing speed can be accelerated through different granularities of parallelism for different applications. Among reconfigurable devices, FPGA (Field-Programmable Gate Array) is the most widely used reconfigurable device. Dynamically rechargeable and configurable FPGA is an important basis for realizing hardware-level multitasking. [0003] The integration of multiple processing cores on a single chip has brought a new challenge, that is, how to connect a large number of on-chip devices....

AI Technical Summary

Problems solved by technology

When there are a large number of on-chip devices, the bus and crossbar connection methods cannot meet the requirements of low latency and high communication traffic inside the chip

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