Chip batch production testing system

Abstract

The invention relates to a chip batch production testing system comprising the following units: a tester 110; the first processor 120 electrically connected with the tester 110 and used for receivinga control order from the tester, configuring a to-be-tested chip according to the control order, and sending the configuration result to the tester 110; the second processor 130 electrically connectedwith the first processor 120 and used for testing the to-be-tested chip according to a testing excitation file sent by the first processor 120. The testing system can finish different test vectors through cooperation of the tester, the first processor and the second processor, thus finishing a batch production test of a complex chip on a low end testing platform, saving the chip batch productiontesting cost, and greatly reducing the testing program developing time; the testing system is convenient in online debug.

Description

technical field [0001] The invention belongs to the technical field of chip testing, and in particular relates to a chip mass production testing system. Background technique [0002] FPGA (Field Programmable Gate Array, referred to as FPGA), that is, field programmable gate array. FPGA and Chengdu are high and small in size, and have the function of realizing special applications through user programming. FPGA can not only solve the shortage of customized circuits, but also overcome the shortcomings of the limited number of gate circuits of the original programmable devices. It is one of the most dynamic and promising technologies in the field of electronic design. [0003] With the wide application of FPGA, its reliability becomes more and more prominent, so the test demand for FPGA becomes particularly urgent. Testing is the most expensive and difficult part of design, and testing will have an increasing impact on product launch time and development cycle. Testing has b...

AI Technical Summary

Problems solved by technology

To complete the configuration test of the test stimulus on the tester side, a high-end tester with a large vector depth is required to complete the test, which will increase the test cost of the chip; while using the SLT test, the test stimulus is generated by the system chip on the test board, which not only saves Storage of test vectors and providing a high-frequency test environment, but the SLT test loses the precise DC parameters and timing parameters of the test machine, and lacks data log information, which is not convenient for subsequent analysis

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