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A Local Jump Instruction Fetching Circuit

A jump instruction and instruction technology, applied in concurrent instruction execution, electrical digital data processing, instruments, etc., can solve the problems of low efficiency of branch instructions, reduce the utilization rate of processor pipeline resources, etc., and achieve the purpose of improving instruction processing throughput, Reduce invalid operations and improve efficiency

Active Publication Date: 2021-07-16
XIAN AVIATION COMPUTING TECH RES INST OF AVIATION IND CORP OF CHINA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0002] In modern processor design, due to the existence of jump and branch instructions, and the branch prediction mechanism is not integrated, the processor is always in a waiting state from the beginning of processing jump and branch instructions to the retrieval and execution of subsequent valid instructions. It reduces the hardware complexity on the premise of ensuring the correct function, but the simplification and directness of this method lead to low efficiency of branch instruction execution, which makes more invalid operations inserted into the processor pipeline, reducing the processor pipeline. resource utilization of

Method used

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  • A Local Jump Instruction Fetching Circuit
  • A Local Jump Instruction Fetching Circuit

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Embodiment Construction

[0018] The technical solutions of the present invention are clearly and completely described below in conjunction with the accompanying drawings and specific embodiments. Obviously, the described embodiments are only a part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative work are all Belong to the protection scope of the present invention.

[0019] see figure 1 , which is a schematic diagram of a partial jump instruction fetching circuit, and the present invention includes a PC update module, a sequential instruction buffer, a retirement instruction buffer and a PC stack.

[0020] The PC update module calculates the next instruction fetch PC according to the execution result of the double-issued instruction. If there is no jump instruction in the double-issued instruction, the PC will be incremented by 1 after executing the 8 inst...

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Abstract

The invention belongs to the technical field of computer hardware and relates to a local jump instruction fetching circuit. The invention includes a PC update module, a sequential instruction buffer, a retirement instruction buffer and a PC stack. The PC update module is responsible for updating the PC address. The retired instruction buffer stores 16 instructions that have been executed. The sequential instruction buffer stores 8 instructions being executed and 8 instructions to be executed. The PC stack is used to save and restore the PC when functions are nested. According to the jump address of the jump instruction, the present invention can realize fast instruction forward partial jump in the retired instruction buffer and backward in the sequential instruction buffer, thereby improving the execution efficiency of the jump instruction and the update efficiency of the buffer instruction, Reduce the waiting delay of the pipeline and improve the execution efficiency of the processor.

Description

technical field [0001] The invention relates to the technical field of computer hardware, in particular to a local jump instruction fetching circuit solution. Background technique [0002] In modern processor design, due to the existence of jump and branch instructions, and the branch prediction mechanism is not integrated, the processor is always in a waiting state from the beginning of processing jump and branch instructions to the retrieval and execution of subsequent valid instructions. It reduces the hardware complexity on the premise of ensuring the correct function, but the simplification and directness of this method lead to low efficiency of branch instruction execution, which makes more invalid operations inserted into the processor pipeline, reducing the processor pipeline. resource utilization. Contents of the invention [0003] The object of the present invention is to provide a partial jump instruction fetching circuit based on a retirement mechanism, and ad...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/30G06F9/38
CPCG06F9/30069G06F9/3804
Inventor 牛少平韩一鹏魏艳艳郝冲邓艺
Owner XIAN AVIATION COMPUTING TECH RES INST OF AVIATION IND CORP OF CHINA
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