High-performance output driving circuit

Abstract

The invention discloses a high-performance output driving circuit, which comprises an output logic unit, a level conversion unit, a buffer unit and an output stage, wherein the output logic unit is used for converting DOUT output by a chip core into two paths of controlled output signals under the control of an enable signal E; THE level conversion unit is used for converting the two paths of controlled output signals with low power supply voltage level of the chip core into two paths of controlled high-voltage output signals with high power supply voltage level of an IO interface circuit, andoutputting the two paths of controlled high-voltage output signals to the buffer unit; the buffer unit is used for increasing driving capacity stage by stage, so as to drive a large-size MOS transistor of the output state; and the output stage is used for transmitting an output signal OUT to a welding pad so as to provide a driving current required for driving a peripheral circuit, and driving anoutput load. By adopting the high-performance output driving circuit, the influence of voltage variations of a parasitic resistor on the operation of an entire output circuit can be effectively reduced when a parasitic capacitor is being charged and discharged by means of a high power supply voltage VCCIO and ground VSSIO of the IO interface circuit, and the reliability of operation of the outputcircuit can be improved.

Description

technical field [0001] The invention relates to an output driving circuit, in particular to a high-performance output driving circuit. Background technique [0002] The IO interface circuit (input and output interface circuit) is widely used in various types of IP circuits, and the normal operation of the IO circuit directly determines the availability of the entire IP circuit. [0003] figure 1 A commonly used prior art output driver circuit is shown, the circuit includes an output logic part, a level conversion part, a buffer part and an output driver tube, wherein the buffer part is only composed of an even number of inverters. The current large-scale integrated circuit signals are becoming more and more complex, and the required PIN pins are increasing. For example, chips such as SRAM only have dozens of input and output PINs, while the overall number of IOs on the chip is limited, and some output PINs are far away from VCCIO and VSSIO PINs. Metal traces are long and i...

AI Technical Summary

Problems solved by technology

The greater the parasitic resistance, the higher the power supply voltage, and the greater the voltage change caused by the parasitic resistance. In severe cases, even the level shifting circuit and buffer circuit of the previous stage cannot work normally, causing the output control signals PS and NS to be embedded. At an interm

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