Step-by-step cyclic etching method for 3D NAND gate line slit trench

A gate line and slit technology, applied in the field of step-by-step cyclic etching, can solve the problems of leakage, bottom W residue, etc., achieve the effect of expanding the window, reducing the generation of void defects, and improving the process quality

Active Publication Date: 2018-05-01
YANGTZE MEMORY TECH CO LTD
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  • Claims
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Problems solved by technology

At the same time, when the shape of the slit trench is tapered, because the bottom width (BCD) of the trench is small, W residues are likely to appear at the bottom in the subsequent process, resulting in leakage

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  • Step-by-step cyclic etching method for 3D NAND gate line slit trench
  • Step-by-step cyclic etching method for 3D NAND gate line slit trench
  • Step-by-step cyclic etching method for 3D NAND gate line slit trench

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Embodiment Construction

[0022] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided for more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0023] In a specific embodiment, the 3D NAND gate line slit trench etching process is improved, and the two etching steps ME1 and ME2 are divided into N steps (N≥2), so that both ME1 and ME2 are Divided into N sub-steps, and then implement the N sub-steps of ME1 and ME2 alternately, so that through the alternate etching of ME1 and ME2, the etching rate of the oxide medium layer and the etching rate of the nitride medium layer are ba...

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Abstract

A step-by-step cyclic etching method for a 3D NAND gate line slit trench is provided. By splitting two etching steps ME1 and ME2 in a 3D NAND gate line slit trench etching process into multiple sub-steps, alternately performing the multiple sub-steps of the ME1 and ME2, and performing an OE step after the sub-steps are performed cyclically, the etching rate of a oxidizing dielectric layer and theetching rate of an nitride dielectric layer are balanced by the alternate etching of the ME1 and ME2. By implementing the step-by-step cyclic etching process, a deep trench structure with good morphology can be obtained, and the window of an etching process is expanded, so that the gate line slit trench is prepared into a good conical morphology, which is beneficial to subsequent injection of thetungsten. Thus, the process quality after a dry etching method is improved, void defects are reduced, and a product yield is improved.

Description

technical field [0001] The present application relates to the technical field of three-dimensional (3D) memory, and more specifically, relates to a step-by-step cyclic etching method for slit trenches of 3D NAND gate lines. Background technique [0002] With the rapid development of flash memory, the structure of 3D flash memory has been developed rapidly, and NAND flash memory is a better storage device than hard disk drives. As people pursue non-volatile storage products with low power consumption, light weight and good performance , 3D NAND flash memory has been widely used in electronic products. [0003] In the 3D NAND structure, the gate line is formed in the slit trench. According to the structural characteristics of the 3D NAND device, the slit trench is an alternate stack structure composed of multiple dielectric layers and multiple sacrificial dielectric layers. It is formed by etching, usually by etching the alternating stack of oxide dielectric layers and nitrid...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/11524H01L27/11551H01L27/1157H01L27/11578
CPCH10B41/20H10B41/35H10B43/20H10B43/35
Inventor 程强乐陶然陈世平刘欢郭玉芳邵克坚张彪
Owner YANGTZE MEMORY TECH CO LTD
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