45results about How to "Optimizing the etch process" patented technology

The present invention generally provides an improved pedestal for supporting a substrate. The pedestal has greatest application during a plasma etching process, such as for a quartz photomask, or “reticle.” The pedestal defines a body, and a substrate support base along an upper surface of the body. The substrate support base has an outer edge, and an intermediate substrate support ridge for receiving and supporting the substrate. At least a portion of the substrate support base outside of the intermediate substrate support ridge is fabricated from a dielectric material. The purpose is to couple greater RF power through the reticle in order to enhance the plasma etching process.

A method and apparatus for process integration in manufacture of a photomask are disclosed. In one embodiment, a cluster tool suitable for process integration in manufacture of a photomask including a vacuum transfer chamber having coupled thereto at least one hard mask deposition chamber and at least one plasma chamber configured for etching chromium. In another embodiment, a method for process integration in manufacture of a photomask includes depositing a hard mask on a substrate in a first processing chamber, depositing a resist layer on the substrate, patterning the resist layer, etching the hard mask through apertures formed in the patterned resist layer in a second chamber; and etching a chromium layer through apertures formed in the hard mask in a third chamber.

The invention discloses a heavy-copper step circuit board and a preparation method thereof. The preparation method comprises the working procedures of primary pattern transfer, pattern electroplating, film removal, secondary pattern transfer, tinning and alkaline etching. The preparation method solves the quality problem of a clamping film and the quality problems such as circuit nicks and unclean etching due to the fact that an anti-corrosion layer cannot be closely bonded with a circuit by a dry film technology by utilizing the production capacity of the available equipment and optimizing roll film, board grinding and etching processes; the whole preparation process is compatible with the traditional circuit board technology; and the quality and the cost can be compatible effectively.

A split gate FET wordline electrode structure and method for forming the same including an improved polysilicon etching process including providing a semiconductor wafer process surface comprising first exposed polysilicon portions and adjacent oxide portions; forming a first oxide layer on the exposed polysilicon portions; blanket depositing a polysilicon layer on the first exposed polysilicon portions and adjacent oxide portions; forming a hardmask layer on the polysilicon layer; carrying out a multi-step reactive ion etching (RIE) process to etch through the hardmask layer and etch through a thickness portion of the polysilicon layer to form second polysilicon portions adjacent the oxide portions having upward protruding outer polysilicon fence portions; contacting the semiconductor wafer process surface with an aqueous HF solution; and, carrying out a downstream plasma etching process to remove polysilicon fence portions.

Etching properties are improved in a processing method of a phase change material in which the regions of one state are removed by etching to form a fine physical pattern. The phase change film is subjected to an advance treatment conducted before the etching, and this advance treatment uses water, an alkaline solution, an acid solution, or a surface-active agent. The regions to be removed by the etching are treated in the advance treatment to facilitate penetration of the etchant in the etching step so that complete removal is accomplished with no film residue. The advance treatment also improves etching resistance of the regions to be left unremoved. The process is thereby stabilized.

The invention relates to a copper cylinder used in the manufacturing process of a circuit board. The copper cylinder is a hollow copper cylinder. Through holes are vertically formed in the side wall of the hollow copper cylinder. Based on the hollow copper cylinder, environment-friendly forming of via holes and embedded holes in a multilayer circuit board can be achieved. According to the forming method of the embedded holes, the hollow copper cylinder is arranged in the circuit board, one end or two ends of the hollow copper cylinder are welded to the circuit board, and accordingly circuits on the two sides of the circuit board can be communicated. Single-layer circuit boards and double-layer circuit boards are laminated to form the multilayer circuit board, and the through holes in the inner-layer circuit board form the embedded holes. When the embedded holes need to be connected with one certain layer of circuit board, the hollow copper cylinder is used, the hollow copper cylinder is inserted into the corresponding positions of the embedded holes from the circuit board at the uppermost layer, tin soldering is performed, and soldering tin is led in through the through holes of the hollow copper cylinder so that soldering tin and the embedded holes of the inner-layer circuit board can be welded. A brand new method for forming via holes and embedded holes in the circuit board is provided, it is hopeful that the etching technology of the circuit board can be overall improved, an electroless plating copper electroplating technology is eliminated, and energy saving and environmental protection are achieved.

The invention discloses a method for embedding a radio frequency chip into a silicon cavity. The method specifically comprises the following steps: 101) a metal column forming step; 102) a cavity manufacturing step; 103) a chip embedding step. The invention provides the method for embedding the radio frequency chip in the silicon cavity, which is convenient to manufacture and simplified in process, and can realize heat dissipation and grounding interconnection at the bottom of the radio frequency chip.

The invention discloses a method for relieving metal residues at a side step of a polycrystalline silicon structure. The method comprises the following steps of forming a polycrystalline silicon layer, and performing photoetching to define a forming area of a polycrystalline silicon structure; etching for the first time in an isotropy way; etching for the second time in the isotropy way, wherein avertical structure is formed at the side step of the polycrystalline silicon structure, and the top part of the vertical structure is of a circular arc structure which is formed during first-time etching; depositing an interlayer film which is formed by stacking common-pressure silicon oxide and boron-phosphorosilicate glass, wherein the thickness of the interlayer film is greater than or equal to the thickness of the vertical structure at the side step of the polycrystalline silicon structure; annealing and refluxing, wherein the boron-phosphorosilicate glass after refluxing forms a completely inclined structure at the side step of the polycrystalline silicon structure; forming an opening in contact with a hole; forming a metal layer, and performing metal etching. The method has the advantage that the boron-phosphorosilicate glass is of the completely inclined structure at the side step of the polycrystalline silicon structure, so as to eliminate the metal residues at the side step of the polycrystalline silicon layer.

The invention discloses a TSV wafer reverse side thinning control method and system based on the vortex technology. The method includes the steps that a vortex sensor is fixed on a transmission shaft of a wafer thinning device and made to be perpendicular to the surface of a wafer and move up and down along with the transmission shaft; an alternating current is applied to the vortex sensor, the thinning device is used for thinning the specific TSV wafer, and a calibration curve of induction signals and distance of the vertex sensor is formulated; an induction signal value of a terminal point is set according to the thinning target distance of the TSV wafer and the calibration curve; the alternating current is applied to the vortex sensor, the thinning device is used for thinning the TSV wafer, and when the induction signals on the vortex sensor reach the set induction signal value, thinning of the reverse side of the TSV wafer is stopped. The TSV wafer reverse side thinning control method and system effectively achieves non-contact measurement, is small in measuring errors, and can accurately control the thickness of the wafer at the bottom of a metal conductive column. The vortex sensor is convenient to install, and low in process cost.

The invention disclosed a method for forming shallow trenches of the dual active regions. Firstly, forming an etch stop layer on a semiconductor substrate; secondly, using a first accurate photomask to expose and develop the semiconductor substrate, until the etch stop layer has been exposed on the top of the first shallow trench regions and the second shallow trench regions; thirdly, etching the etch stop layer entirely in the exposed regions; fourthly, using a second photomask to expose and develop the first shallow trench regions which require a deeper etch depth of the trench than that of the second shallow trench regions; fifthly, etching and forming preliminary entirely depth in the first shallow trench regions, and then removing the second photomask; at last, taking the etch stop layer as a mask, and simultaneously etching the first shallow trench regions and the second shallow trench regions to form the first hallow trenches and the second shallow trenches having different depths. The invention has realized a low-cost photomask application and an optimization of the etching process by optimizing the photomask design.

The invention discloses a groove type wet etching device. The device comprises a process tank and at least one acid liquor supply tank, a connecting duct and a support member, wherein the position ofthe process tank is lower than that of the acid liquor supply tank; wherein the acid liquor supply tank is communicated with the process tank through a connecting pipeline; the connecting pipeline atleast comprises a transverse pipeline and a longitudinal pipeline which are connected; the inlet end of the transverse pipeline is connected with the acid liquor supply tank; wherein the outlet end ofthe longitudinal pipeline is connected with the process tank, the acid liquor supply tank is used for storing acid liquor and supplying the stored acid liquor into the process tank through the connecting pipeline, and the process tank is used for diluting the acid liquor supplied by the acid liquor supply tank or mixing a plurality of supplied acid liquors so as to carry out an etching process; and the supporting part is in contact with the transverse pipeline and is used for keeping the transverse pipeline horizontal. The groove type wet etching device ensures that the concentration of the acid can be kept stable after each time of acid change.

The invention provides a manufacturing method of a fin field effect transistor. The method includes: forming a source region and a drain region on the surface of a silicon substrate; forming an oxidelayer on the surface of the silicon substrate and performing planarization processing on the oxide layer to enable the source region and the drain region to be exposed; etching the oxide layer in a channel region between the source region and the drain region, and removing the oxide layer in the channel region; forming an epitaxial layer on the surface of the oxide layer, and performing etching-back processing on the epitaxial layer, wherein the channel region is filled with the epitaxial layer; etching the oxide layer at two sides of the epitaxial layer in the channel region; forming a gate dielectric layer on the surface of the epitaxial layer of the channel region, wherein the gate dielectric layer covers the source region, the drain region and the channel region; and forming a gate onthe surface of the gate dielectric layer. The invention also provides a fin field effect transistor manufactured by employing the above method.