TSV wafer reverse side thinning control method and system based on vortex technology

Abstract

The invention discloses a TSV wafer reverse side thinning control method and system based on the vortex technology. The method includes the steps that a vortex sensor is fixed on a transmission shaft of a wafer thinning device and made to be perpendicular to the surface of a wafer and move up and down along with the transmission shaft; an alternating current is applied to the vortex sensor, the thinning device is used for thinning the specific TSV wafer, and a calibration curve of induction signals and distance of the vertex sensor is formulated; an induction signal value of a terminal point is set according to the thinning target distance of the TSV wafer and the calibration curve; the alternating current is applied to the vortex sensor, the thinning device is used for thinning the TSV wafer, and when the induction signals on the vortex sensor reach the set induction signal value, thinning of the reverse side of the TSV wafer is stopped. The TSV wafer reverse side thinning control method and system effectively achieves non-contact measurement, is small in measuring errors, and can accurately control the thickness of the wafer at the bottom of a metal conductive column. The vortex sensor is convenient to install, and low in process cost.

Description

technical field [0001] The invention relates to the technical field of microelectronics, in particular to a thinning control method and system on the back of a TSV wafer based on eddy current technology. Background technique [0002] With the continuous advancement of microelectronics technology, the feature size of integrated circuits has been continuously reduced, and the interconnection density has been continuously increased. At the same time, users' requirements for high performance and low power consumption have been continuously increased. In this case, the way to improve the performance by further reducing the line width of the interconnection is limited by the physical characteristics of the material and the equipment process, and the resistance-capacitance (RC) delay of the two-dimensional interconnection gradually becomes the limit to improve the performance of the semiconductor chip. bottleneck. [0003] The Through Silicon Via (TSV) process can realize direct t...

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Problems solved by technology

[0008] Although the above two methods can calculate the distance from the bottom of the conductive metal pillar to the back of the wafer by measuring the thickness of the entire wafer, in the specific process, the depth of the hole on the wafer and the depth of the deposition of the conductive metal pillar will vary. Therefore, the above method cannot accurately obtain the distance from the bottom of the conductive metal pillar to the back of the wafer, which will have a certain impact on the subsequent etching and other processes.

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