Method of fabricating high-k/metal gate device

Abstract

The present disclosure provides a method that includes providing a semiconductor substrate; forming a gate structure over the semiconductor substrate, first gate structure including a dummy dielectric and a dummy gate disposed over the dummy dielectric; removing the dummy gate and the dummy dielectric from the gate structure thereby forming a trench; forming a boundary layer on the semiconductor substrate; forming a high-k dielectric layer on the boundary layer partially filling the trench; forming a barrier layer over the high-k dielectric layer partially filling the trench; forming an capping layer over the barrier layer partially filling the trench; performing an annealing process; removing the capping layer; forming a metal layer over the barrier layer filling in a remainder of the trench; and performing a chemical mechanical polishing (CMP) to remove the various layers outside the trench. The invention can improve the quality of the high-k dielectric layer in the final component.

Description

technical field [0001] The invention relates to a method for manufacturing a semiconductor element, in particular to a method for manufacturing a high-permittivity dielectric layer and / or a metal gate element. Background technique [0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have resulted in the evolution of generations of ICs, each with smaller and more complex circuits than the previous generation. However, the aforementioned advancements have increased the complexity of manufacturing ICs and processes, and in order for these advanced technologies to be realized, the development of similar IC processes and fabrications is necessary. [0003] In the course of IC evolution, the density of functions (i.e., the number of devices interconnected per chip area) has gradually increased, while the geometry size (i.e., the smallest element (or line) that can be created using a process) ha...

AI Technical Summary

Problems solved by technology

In view of this, in the CMOS technology manufacturing process, one or more thermal process cycles (such as dummy polysilicon thermal step, interstitial thermal step, and source and drain activation steps) can cause the high-k gate The quality of the dielectric layer degrades

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