Data receiving method and device based on serial Flash controller
A technology for receiving data and controllers, applied in the field of communication, can solve problems such as difficult to meet high-speed data transmission and low serial clock frequency, and achieve the effect of speeding up data transmission and increasing the rate
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Embodiment 1
[0046] Embodiment 1 of the present invention provides a method for receiving data based on a serial Flash controller, such as figure 1 As shown, the method includes:
[0047] S101, when the serial Flash controller receives the input data sent by the flash memory Flash chip, obtain the value of the sampling selection register, determine the sampling delay time according to the value of the sampling selection register and the second working clock signal; the second The working clock signal is the working clock signal of the serial Flash controller;
[0048] Here, the method further includes: sending a preset first working clock signal to the flash memory Flash chip; wherein, the frequency of the first working clock signal is lower than the frequency of the second working clock signal.
[0049] Before the serial Flash controller receives the input data output by the Flash chip from the Flash chip, the serial Flash controller sends the first working clock signal to the Flash chip...
Embodiment 2
[0071] In the embodiment of the present invention, the method for receiving data based on the serial Flash controller provided by the embodiment of the present invention is described by taking QSPI as an example. QSPI is an extension of the SPI interface. As a serial Flash controller, it supports NorFlash operation And NandFlash operation. In this embodiment, the bit width of the clock buffer selection register for illustration is 3 bits, which can be expressed as clkbufsel[2:0], and the bit width of the data delay selection register is 5 bits, which can be expressed as datdlysel[4:0] ], the bit width of the sampling selection register is 3 bits, which can be expressed as samplesel[2:0].
[0072] Such as figure 2 As shown, 8 clock buffers clkbuf are connected in series to form a clkbuf chain, and the clkbufsel register is set to select which stage of the 8-stage delay buffer selection register is output, and the delay range is 1-8 clock buffers.
[0073] Such as image 3 A...
Embodiment 3
[0080] In order to achieve the above, the embodiment of the present invention also provides a device for receiving data based on a serial Flash controller, such as Figure 4 As shown, the device includes: a sampling delay unit 401, a sampling selection unit 402 and a sampling unit 403, wherein,
[0081] Sampling delay unit 401 is used to obtain the value of sampling selection unit 402 when the serial Flash controller receives the input data sent by the flash memory Flash chip, and determine the sampling delay according to the value of the sampling selection unit and the second operating clock signal time; the second working clock signal is the working clock signal of the serial Flash controller;
[0082] The sampling unit 403 is configured to adjust the sampling start time according to the sampling delay time to perform sampling to receive the input data; wherein, the sampling start time is to use the second working clock signal as the sampling signal to start the Flash The m...
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