A method and device for detecting data dependence between instructions

Abstract

The embodiment of the invention discloses a method and device for detecting data dependence between instructions. The method includes: when a detection thread is accessing the variable, detecting whether there is a historical access operation to the variable, if there is no historical access operation to the variable, recording the thread number of this access operation, otherwise, if This access operation is a write operation. Compare the thread number of the historical access operation with the thread number of this access operation. If the thread number of this access operation is smaller than the thread number of the historical access operation, it indicates that the instruction to be detected has data dependence and terminates. Detection, if this access operation is a read operation and the historical access operation includes historical write access operations, compare the thread number of the historical write access operation with the thread number of this access operation, if the thread number of this access operation is less than the historical write access operation The thread number of the operation indicates that there is data dependence in the instruction to be detected, and the detection is terminated.

Description

technical field [0001] Embodiments of the present invention relate to the field of computers, and in particular, to a method and device for detecting data dependence between instructions. Background technique [0002] In recent years, many-core computing is not only applied to high-performance computing, but also many-core computing technology represented by Graphics Processing Unit (GPU) can be found everywhere on mobile devices and personal computers. However, accelerating existing programs using heterogeneous many-core processors remains a challenging task. Since loops often consume a large proportion of execution time in serial programs, loop parallelization is a scheme to accelerate existing programs by using many-core accelerators. Among loop parallelization schemes, the polyhedron model is a powerful solution for analyzing loops and converting loops to many-core processors, and compilers based on the polyhedron model are emerging in an endless stream. However, the p...

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Problems solved by technology

However, the polyhedron model can only analyze loops whose iterative domain and data domain are all affine functions, and there are still a large proportion of non-affine dynamic loops in the iterative domain or data domain that exist in a variety of existing programs

Since such loops may have compile-time indeterminate data dependencies, they are difficult to parallelize using polyhedral models or other static means

[0003] However, judging the data dependencies between iterations at runtime may consume a lot of extra time and space, resulting in the entire loop being placed on the GPU without a good speedup ratio, and even because the space requirement is too high, it cannot be placed in the memory. Execution on scarce GPU

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