Anti-single event flip protection method for dual-core arm processor based on zynq-7000

An ARM processor, anti-single event technology, applied in the direction of electric digital data processing, instrumentation, response error generation, etc., can solve the problems of complex fault detection and failure to realize fault recovery, etc., achieve simple process, reduce calculation loss, The effect of ensuring reliable operation

Active Publication Date: 2021-11-02
HARBIN INST OF TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] The present invention is to solve the problem that the dual-mode redundancy method can only realize fault detection, but cannot realize fault recovery, and the existing fault detection is complicated

Method used

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  • Anti-single event flip protection method for dual-core arm processor based on zynq-7000
  • Anti-single event flip protection method for dual-core arm processor based on zynq-7000

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specific Embodiment approach 1

[0030] Specific implementation mode one: see figure 1 Illustrate this embodiment, the Zynq-7000-based dual-core ARM processor anti-single event flip protection method described in this embodiment, the method includes the following steps:

[0031] The dual-core mutual inspection method is used to detect the error of the program executed by the dual-core, and then roll back the detected error to realize the error recovery.

[0032] In this embodiment, the program executed by the dual-core is an application program of the on-board software.

specific Embodiment approach 2

[0033] Specific implementation mode two: see figure 2 Describe this embodiment, the difference between this embodiment and the Zynq-7000-based dual-core ARM processor anti-single event reversal protection method described in the first embodiment is that the dual-core mutual inspection method is used to check the program executed by the dual-core Error detection, and then rollback recovery of detected errors, the specific process of realizing error recovery is:

[0034] Step 1: the dual cores are respectively defined as CPU0 and CPU1, and the input of CPU0 is copied to CPU1 to ensure that the two have the same input information; the same program is executed in the CPU0 and CPU1, and the program is divided into m-1 segments, The end of each segment is a checkpoint, the sequence number of the checkpoint is i, the initial value of i is 1, i is an integer, and m is an integer greater than 3;

[0035] Step 2: In CPU0 and CPU1, execute in parallel from the position where the curren...

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Abstract

A Zynq-7000-based dual-core ARM processor anti-single event flip protection method belongs to the field of processor anti-radiation hardening. It solves the problems that the dual-mode redundancy method can only realize fault detection, but cannot realize fault recovery, and the existing fault detection is complicated. The method of the present invention includes the following steps: using the dual-core mutual inspection method to perform error detection on the programs executed by the dual-core, and then rewinding and recovering the detected errors to realize error recovery. It is mainly used for error detection and recovery of programs executed by dual cores.

Description

technical field [0001] The invention belongs to the field of processor radiation resistance reinforcement. Background technique [0002] Using Commercial Off The Shelf (COTS) FPGA products to develop small satellites and microsatellites is a new development direction of satellite technology. Among them, Xilinx Zynq-7000 SoC chip is a product of the continuous development of heterogeneous multi-core SoC. It embeds dual-core ARM processor, programmable logic and hard IP peripherals in the same chip. Widely concerned in the field of satellites, and gradually applied to engineering practice in the field of aerospace. [0003] The PS (Process System) part of the Zynq chip integrates a dual-core Cortex-A9ARM processor, which can use an asymmetric multi-processing (Asymmetric Multi-core Processor, AMP) mechanism to execute different tasks in parallel or redundantly to maximize system performance. change. However, as a COTS device, Zynq has low radiation resistance and is easily ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F11/14G06F11/20
CPCG06F11/1415G06F11/2028
Inventor 崔秀海沈露张晓曦彭宇彭喜元
Owner HARBIN INST OF TECH
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