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Management method, system and equipment of memory chip and storage medium

A storage chip and management method technology, applied in the storage field, can solve problems such as execution errors, achieve the effects of reducing error rates, increasing read and write speeds, and reducing read and write operation time

Inactive Publication Date: 2018-05-29
GIGADEVICE SEMICON (BEIJING) INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] Embodiments of the present invention provide a memory chip management method, system, device, and storage medium, which solves the technical problem that execution errors are easily caused by performing operations such as garbage collection interspersed in the reading and writing process, and realizes high-efficiency reading of the memory chip. Write

Method used

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  • Management method, system and equipment of memory chip and storage medium
  • Management method, system and equipment of memory chip and storage medium

Examples

Experimental program
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Embodiment 1

[0039] figure 1 It is a schematic flow chart of a memory chip management method provided by Embodiment 1 of the present invention. This embodiment is applicable to the situation where memory chips are managed in idle time. This method can be executed by a memory chip management system. The system It can be implemented in the form of software and / or hardware.

[0040] Such as figure 1 Described, the method of the present embodiment comprises:

[0041] S110. Obtain the time interval between the current time and the time when the host command was received last time.

[0042] Optionally, obtaining the time interval between the current time and the time when the host command was received last time includes: obtaining the historical time corresponding to the previous host command received and the current time, and calculating the current time distance according to the historical time and the current time The time interval when the host command was last received.

[0043] Conside...

Embodiment 2

[0057] figure 2 It is a schematic flowchart of a preferred example of a memory chip management method provided by an embodiment of the present invention. This implementation is a preferred embodiment of Embodiment 1, and the specific steps of the management method of the memory chip are:

[0058] S210. Whether no command from the host is received within 200 ms, if yes, perform S220.

[0059] Specifically, the time interval for not receiving a host command can be obtained according to the current time and the last time the host command was received, and if the time interval exceeds a preset time interval, for example, the preset time interval can be 200ms, then enter sleep In the preparation mode, it starts to judge whether the preset management rules are met.

[0060] S220. Determine whether to perform garbage collection operation, if yes, execute S230, otherwise, execute S240.

[0061] Specifically, it is judged whether the number of free blocks of the memory chip is lowe...

Embodiment 3

[0074] image 3 It is a schematic structural diagram of a memory chip management system provided by Embodiment 3 of the present invention, and the system includes: an acquisition module 310 and a processing module 320 .

[0075] Among them, the obtaining module 310 is used to obtain the time interval between the current time and the time when the host command was received last time; the processing module 320 is used to determine that the memory chip meets the preset time interval threshold when If the management condition is set, the target management operation corresponding to the management condition is executed; wherein, the target management operation includes a garbage collection operation, a wear leveling operation and / or an erasing operation.

[0076] In the technical solution of the embodiment of the present invention, by obtaining the time interval between the current moment and the time when the host command was received last time, since the chip may enter the sleep ...

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Abstract

The invention discloses a management method, a system and equipment of a memory chip and a storage medium. The method includes the steps that the time interval is acquired between the current time andthe last time a host command is received; when it is detected that the time interval exceeds the preset time interval threshold, if the memory chip is judged to meet the preset management conditions,and the target management operation corresponding to the management conditions is executed; wherein the target management operation comprises a garbage recovery operation, a loss balancing operationand / or an erasure operation. According to the technical scheme, the technical scheme is solved that the speed of reading and writing is decreased due to alternately executing garbage collection andother operations in the process of reading and writing, the existing management method of the memory chip is optimized, and the efficient read-write of the storage chip is achieved.

Description

technical field [0001] Embodiments of the present invention relate to the field of storage technology, and in particular, to a management method, system, device, and storage medium for a storage chip. Background technique [0002] During the use of chips in eMMC (Embedded Multi Media Card), due to the limitation of the total number of physical block blocks, there will be fewer and fewer blocks that have not been programmed, and among the blocks that have been programmed, Not all are valid data. In order to have enough blocks for programming, there are two implementation methods. The first implementation method is garbage collection operation, which is to find those blocks with data and less valid data as source blocks, and collect the valid data of source blocks. , move to another destination block, and then release the source block, so that there are enough blocks for use; the second implementation mode is the wear leveling operation, that is, when the data stored in a cer...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F3/06
CPCG06F3/0616G06F3/0629G06F3/0644G06F3/0652
Inventor 刘凯
Owner GIGADEVICE SEMICON (BEIJING) INC
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