A method to reduce the stress effect of MOS tube

Abstract

The invention discloses a method for reducing the stress effect of MOS transistors, which belongs to the technology in the field of semiconductor processing, including: step S1, performing a first implantation process on the source and drain preparation region with a first particle; step S2, performing a second implantation process on the source-drain preparation region with a second particle; step S3, performing a third implantation process on the source-drain preparation region with a third particle; step S4, performing a third implantation process on the source-drain preparation region; The heat treatment process is performed in the drain preparation area. The beneficial effect of the technical solution is that the invention increases the ion concentration in the source region or the drain region formed after ion implantation, and reduces the stress effect in the MOS tube.

Description

technical field [0001] The invention relates to a technology in the field of semiconductor processing, in particular to a method for reducing the stress effect of a MOS tube. Background technique [0002] The Shallow Trench Isolation (STI) process was first produced in the 1980s, but initially had problems of high cost and imperfect process technology, and it was not widely accepted and cited until the end of the last century. The shallow trench isolation process is different from the previous processing technology. It is a new type of isolation technology that is completely flat, and the shallow trench isolation technology completely avoids the high temperature process problems used in the previous processing technology; The effective area of ​​the source region; in addition, the surface of the silicon substrate and the surface of the isolation medium are completely on the same plane; in addition, the shallow trench isolation technology also improves the problem of junction...

AI Technical Summary

Problems solved by technology

However, after adopting STI technology, there will be stress effect

Stress effect (LOD effect) means that STI isolation produces amorphous or uneven biaxial compressive stress, which leads to uneven stress distribution in the active area, affects the diffusion of ions in the active area, and further affects the electrical properties of the device. performance is adversely affected

[0005] At present, the common method to improve the LOD effect is to change the wiring design, but this method will reduce the integration of MOS transistors

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