Dynamic alignment method of FPGA multi-channel serial data based on training sequence

Abstract

The invention discloses a dynamic alignment method of FPGA multi-channel serial data based on a training sequence. The method is as follows: performing a serial-to-parallel conversion operation on high-speed serial data of channels; detecting and compensating offsets of clock latching edges and data centers of the channels, and performing bit alignment; performing a sliding operation on the outputparallel data, and performing byte alignment; and performing the same delay on the parallel data output by the channels, and performing channel alignment. According to the method, dynamic alignment of the FPGA multi-channel high-speed serial data is achieved by using a training word as reference, and the alignment mainly comprises bit alignment, byte alignment and channel alignment. By adoption of the dynamic alignment method, the reception of multi-channel high-speed data is more flexible, the alignment operation can be automatically performed on data lines and clock lines of the channels inreal time according to the physical state of a current transmission system, the change in an external environment is continuously adapted, the reliable transmission and reception of data are ensured,and the transportability is good.

Description

technical field [0001] The invention belongs to the field of high-speed digital image signal processing, and in particular relates to a training sequence-based FPGA multi-channel serial data dynamic alignment method. Background technique [0002] With the higher resolution and higher data throughput of digital image processing systems, the data transmission system is developing towards multi-channel and ultra-high-speed transmission. In the multi-channel high-speed digital image signal transmission process, due to the reduction of the data window, the different transmission path delays of each channel and the change of external environmental conditions (such as temperature), the data signal and clock signal of each channel are in the receiving end of the FPGA. Out of synchronization, that is, bit offset, word offset and channel offset occur, which affects the reliability and stability of receiving digital image signals. And as the data transmission rate of each channel cont...

AI Technical Summary

Problems solved by technology

However, the static phase adjustment process will consume a lot of labor and time, and the static parameters set are only for the physical state of the current board, and cannot adapt to changes in external environmental conditions in time

At the same time, under some special conditions, such as limited PCB size, it is difficult to implement strict equal-length wiring, and there will still be offsets between channels, which is extremely unfavorable for the processing of back-end digital signals. Especially in the field of image processing

To sum up, the static phase adjustment technology has shortcomings such as time-consuming, many limitations, poor portability, and susceptibility to external environmental interference, which cannot completely solve the problem of multi-channel data transmission offset.

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