No-Snapback silicon controlled rectifier type ESD protection structure and realization method thereof

Abstract

The invention discloses a no-Snapback silicon controlled rectifier type ESD protection structure and a realization method thereof. The structure comprises: a semiconductor substrate (80); and an N-well (60) and a P-well (70) that are generated on the semiconductor substrate. A high-concentration P-doped layer (20) and a high-concentration N-doped layer (28) are arranged above the N-well (60). Thehigh-concentration P-doped layer (20), the N-well (60) and the P-well (70) form an equivalent PNP triode structure. A high-concentration N-doped layer (24) and a high-concentration P-doped layer (26)are arranged above the P-well (70). The N-well (60), the substrate (80) / the P-well (70) and the high-concentration N-doped layer (24) form an equivalent NPN triode structure. A high-concentration N-doped layer (22) is arranged above a boundary between the N-well (60) and the P-well (70). A portion of the N-well (60) is arranged between the high-concentration P-doped layer (20) and the high-concentration N-doped layer (28), and the distance between the high-concentration P-doped layer (20) and the high-concentration N-doped layer (28) is S. A portion of the N-well (60) is arranged between the high-concentration N-doped layer (28) and the high-concentration N-doped layer (22).

Description

technical field [0001] The invention relates to the technical field of semiconductor integrated circuits, in particular to a novel silicon-controlled rectifier-type ESD protection structure without hysteresis effect and a realization method thereof. Background technique [0002] The anti-static protection design of high-voltage circuits has always been a technical problem, because the core of high-voltage circuits: high-voltage devices (such as LDMOS) are not suitable for anti-static protection design like ordinary low-voltage devices, because the hysteresis effect curve of high-voltage devices The exhibited characteristics are poor. Such as figure 1 as shown, figure 1 It is the hysteresis effect curve of a high-voltage device LDMOS with a working voltage of 32V, from figure 1 It can be concluded that: 1) the trigger voltage (Vt1) is too high; 2) the holding voltage (Vh) is too low, often far lower than the operating voltage of the high-voltage circuit, and it is easy to ...

AI Technical Summary

Problems solved by technology

The low-voltage PMOS device is a common electrostatic protection device without hysteresis effect, because the parasitic PNP transistor current gain is relatively small when the hysteresis effect occurs, but the shortcoming of the low-voltage PMOS device is the secondary breakdown of the hysteresis effect The current (It2) is relatively small, so the industry has been researching and developing an anti-static protection device that has no hysteresis effect and has a high secondary breakdown current.

However, the disadvantage of the existing silicon-controlled rectifier without hysteresis effect is that the device size is relatively large, especially when several stages are required to be connected in series, the layout area is relatively large

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