FFT reuse method

A technology of multiplexing processing and data, applied in the field of signal processing, can solve the problems of occupied resources, fast and difficult parallel processing operation, and achieve the effect of balancing contradictions, optimizing the occupation of logic resources, and reducing the complexity of system processing.

Active Publication Date: 2018-06-26
NO 8511 RES INST OF CASIC
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Parallel processing is faster and takes up more resources, which is especially difficult for some systems with tight space and hardware resources.

Method used

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Embodiment

[0036] Set a 64-channel filter bank (K=64), the high-speed signal sampling rate fs is 2.6GHz, the external AD is divided into 8 phases (8-fold extraction, D=8) and enters the FPGA, and the data rate of each phase is 325MHz, that is, the FPGA runs The rate is 325MHz; the filter bank output rate fo=fs / 64=40.625MHz, the multiplexing multiple of each phase data=fpga operation rate / output rate=325 / 40.625=8, that is, 8 times multiplexing; the specific steps are as follows:

[0037] Step 1, perform D-fold extraction according to the high-speed sampling data input from the outside, and perform digital filtering on each item of extracted data;

[0038] Step 11, first divide the input 2.6GHz high-speed sampling data into 8 phases and perform FPGA acquisition and latching;

[0039] Step 12, each phase data is extracted by 8 times;

[0040] Step 13, prepare for equivalent extraction of the FIR low-pass filter coefficients according to the 8-fold extraction sampling data;

[0041] Step 1...

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Abstract

The invention provides an FFT reuse method. The method comprises the steps that 1, D-fold extraction is performed according to externally input high-speed sampling data, and digital filtering is performed on each piece of extracted data; 2, in K/D continuous clock cycles, e<-2(pi)k/K> frequency shift processing is performed on filtered output data; 3, in the K/D continuous clock cycles, serial-to-parallel conversion is performed on the obtained data, and the data is updated once in each K/D clock cycle; 4, D-point parallel FFT processing is performed on D-point data, and reuse processing is performed on an FFT result in each of the K/D clock cycles; and 5, K-point FFT results jointly composed of the D-point FFT results obtained in each cycle are rearranged and sequentially output accordingto an engineering demand.

Description

technical field [0001] The invention relates to a signal processing technology, in particular to an FFT multiplexing method. Background technique [0002] Fast Fourier transform (FFT) is a fast algorithm of discrete Fourier transform (DFT). It is an important mathematical tool to describe the relationship between time domain and frequency domain of discrete signals, and is widely used in digital signal processing. The traditional FFT algorithm can be implemented by software, DSP, dedicated FFT processing chip or FPGA. Among them, the speed of software and DSP is relatively slow, which cannot meet the requirements of real-time processing of high-speed signals in digital receivers; although the speed of dedicated FFT processing chips is fast, it is expensive and difficult to be widely promoted. FPGA has abundant resources, fast speed, and flexible design, and has been widely used in recent years. [0003] At present, the design scheme of FFT processor implemented by FPGA can...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/14
CPCG06F17/141
Inventor 陈望杰鲍成浩李仙法张健伟杨健吴鸿海靳东
Owner NO 8511 RES INST OF CASIC
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