Generation method for module interface verification assembly

Abstract

The invention discloses a generation method for a module interface verification assembly. The method is characterized by comprising the following steps that 1, an interface verification assembly template with a correct function which is determined through verification is adopted, and special marks are adopted for positions, related to signal usage, in a verification assembly file of the template;2, an interface verification assembly generation module reads an interface signal configuration file, then the special marks in the interface verification assembly template are replaced by signals inthe interface signal configuration file according to input configuration, assembly interface behavior codes of the signals are completed, and accordingly a whole verification assembly of an interfaceis generated; 3, the first step and the second step are repeated, and module interface verification assemblies of all interfaces are completed. According to the method, the quality difference of an interface basic assembly due to the experience difference of all verification personnel is avoided, the item verification efficiency is improved, the development period is shortened, and the implementation quality of the verification assemblies is improved.

Description

technical field [0001] The invention belongs to the field of digital chip development, in particular to a method for generating a module interface verification component applied to a digital chip verification platform. Background technique [0002] At present, the integration degree and main frequency speed of digital ASIC (Application Specific Integrated Circuit, ASIC) are developing at a high speed according to Moore's theorem, doubling every two years, and the development scale is also developing at a high speed. Algorithm chips such as GPU and encryption and decryption algorithms With a higher and higher development and integration scale, as the complexity of the chip increases, the digital chip verification work will also face huge challenges. More and more complex chip development will involve multi-module division, and various common or custom communication protocol interfaces will inevitably be involved between modules. Verifiers of each module will face a large numb...

AI Technical Summary

Problems solved by technology

The main problem with the development method of the original interface verification component is low efficiency. After developing an interface component, it is necessary to verify its correctness and modify it to solve the problems existing in the development due to lack of experience or poor consideration. After the development is completed Then develop a similar process for the next interface

In the development process, it is easy to rework due to imperfect components. Even if experienced verification personnel have less rework, the time period required for interface-by-interface development will be longer, which will affect the efficiency of module verification and seriously affect the verification efficiency of the project as a whole.