Wafer level metal shielded packaging structure and manufacturing method thereof

Abstract

The invention discloses a wafer level metal shielded packaging structure and a manufacturing method thereof. According to the method, in the re-routing and bump manufacturing process, a first conductive structure electrically connected with a chip unit is formed, the front surface of the chip unit is further provided with one or more second conductive structures at the position adjacent to the side surface, the second conductive structures are not conducted with a circuit of the chip unit, a metal shielding layer connected with the second conductive structures is formed at the back and the side edges of the chip unit after the chip unit is cut, the chip unit can be directly installed on a substrate, the second conductive structures are enabled to be electrically connected with a groundingstructure of the substrate, and the metal shielding layer is connected so as to generate a metal shielding effect, so that elements can be effectively prevented from being subjected to electromagneticinterference, and a purpose of reducing the size of the elements is achieved at the same time.

Description

technical field [0001] The invention relates to a wafer-level chip-scale package (WLCSP) structure, in particular to a wafer-level metal-shielded package structure and a manufacturing method thereof which have a metal shielding effect and effectively realize component volume reduction. Background technique [0002] The existing wafer-level chip size package (WLCSP) is applied to the anti-electromagnetic wave design of reducing electromagnetic interference (EMI), mainly after the active and passive components are placed on the board, and the active and passive components are molded with plastic materials. Cover, and then use metal sputtering or add a metal cover to cover it and connect it to the ground wire to achieve EMI protection. These technologies will increase the thickness and volume of the finished product. For existing 3C products and wearable devices, the volume requirements are very high, which does not meet the trend and demand of light, thin and short. [0003] ...

AI Technical Summary

Problems solved by technology

This manufacturing process increases the restrictiveness of the operation and is relatively cumbersome. In addition to affecting the yield, it will also increase the production cost and prolong the production cycle; in addition, because the additional conductive bumps 3 are arranged around the chip unit 2, the volume of the component increases. Large, but also affect the cost and pass rate

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