Wafer packaging method and packaging structure

Abstract

The invention provides a wafer packaging method and packaging structure. The method comprises the steps of: providing a device wafer, forming a plurality of first chips in the device wafer, and forming first electrodes on the first chips; forming first dielectric layers and first conductive bumps on the device wafer, the surfaces of the sides, far away from the first chips, of the first dielectric layers and the first conductive bumps being flush; forming second electrodes on second chips; forming second dielectric layers and second conductive bumps on the second chips, the surfaces of the sides, far away from the second chips, of the second dielectric layers and the second conductive bumps being flush; aligning and bonding the second dielectric layers and the first dielectric layers as well as the second conductive bumps and the first conductive bumps; forming an insulating layer covering the first dielectric layer, the second chips, and the second dielectric layers, the second electrodes and the second conductive bumps exposed out of the second chips in a shape-preserving manner; covering the insulating layer with a shielding layer in a shape-preserving manner; and forming a packaging layer on the shielding layer. According to the invention, the packaging method is simplified, and the size of the formed packaging structure is reduced.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a wafer packaging method and a packaging structure. Background technique [0002] System-in-Package Sip (System in Package) can combine multiple active components with different functions, as well as other components such as passive components, micro-electromechanical systems (MEMS), and optical components, into one unit to form a multi- Functional systems or subsystems that allow integration of heterogeneous ICs. It effectively solves the problem that SOC (system-on-chip) cannot integrate analog, radio frequency and digital functions. System-in-package SiP integration is relatively simple, the design cycle and market cycle are shorter, the cost is lower, and more complex systems can be realized. [0003] WLP mainly includes two important processes of physical connection and electrical connection. For example: the physical connection between the chip to be integrated an...

AI Technical Summary

Problems solved by technology

For example: the physical connection between the chip to be integrated and the wafer is realized by bonding technology, the electrical connection between semiconductor devices is realized by electroplating technology, and the chip to be integrated is realized by through-silicon via (TSV) and electroplating technology The electrical connection with other circuits, the packaging method is relatively complicated; and the chip to be integrated is easily affected by the external magnetic field during the use of the packaging structure, resulting in the problem of unstable performance. Therefore, in the packaging process, usually The interference of the external magnetic field is reduced by setting a shielding structure in the packaging structure, but the packaging structure with shielding function has the problem of large volume and thickness

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