A kind of adc-based start-up deterministic delay system and method

Abstract

The invention discloses a power-on certainty delay system and method based on an ADC, and relates to the technical field of the time calibration. The system comprises a reference clock source connected with a power divider, the power divider is connected with a frequency synthesizer and an analog switch, the frequency synthesizer is connected with the ADC and a coherent synchronization address generator; the analog switch is connected with a target signal input port and the ADC, the ADC is connected with a cache, and the cache is connected with a delivery calibration memory, a delay numericalvalue computing module and a delay compensation module; the coherent synchronization address generator is connected with the delivery calibration memory, the delivery calibration memory is connected with the delay numerical value computing module, and the delay numerical value computing module is connected with the delay compensation module. The system disclosed by the invention has the advantagesthat the self-calibration is performed after the system is powered on, the delay of a data link in the system maintains unchanged after each power-on, thereby guaranteeing ranging precision of a phased array system without increasing the complicated hardware calibration network, the equipment quantity and the hardware cost.

Description

technical field [0001] The present invention relates to the technical field of time calibration, and more particularly relates to an ADC-based deterministic startup delay system and method. Background technique [0002] In the phased array receiving system of modern radar and communication, the number of antenna units is large and the instantaneous bandwidth of the signal is large, so it is necessary to use multiple high-speed analog-to-digital converter (Analog-to-Digital Converter, ADC) chips to complete the analog-to-digital conversion of the received signal , in order to perform processing such as wave velocity formation and anti-interference in the digital domain. In a large-scale phased array system, there are thousands or even tens of thousands of ADC chips, and they are distributed in different sub-array units, extensions, plug-ins or modules. For large-scale array data acquisition systems that are even higher than high-speed ADCs, there are a series of channel inco...

AI Technical Summary

Problems solved by technology

Its disadvantage is that it needs to increase the complex hardware correction network, which increases the amount of equipment and hardware cost, especially for large-scale systems, and some systems do not allow the receiver to use the transceiver closed-loop correction process every time it is turned on, so as not to affect the normal operation of the task. implement

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